成都招聘

Ideal Candidate

Candidate is preferred to be MS EE with minimum of 3+ year, or BS EE with minimum of 5+ years experience in digital ASIC/SOC design verification. Can help manager to execute plans in projectwith high quality results.Strong communication capability in English is required.

Your daily work such as...

-Work with global architecture and designers to get a full deep insight on the design under verification.

-Unit/Block/Cluster/Chip level state of the art verification, test bench setup/maintain and methodologydeployment.

-Test case creation to ensure coding coverage meet target.

-Provide clear status ofchip verification progress and issues to management.

-Support DFX verification

 

We hope you are...

-Has learnt knowledge of Verilog/C/C++/System C/System Verilog

-Verification of large scale ASICs

-Can understand on Object Oriented verification such as UVM/OVM.

-Knowledge of low-power design technique and implementation flow is plus

-Strong cooperation skill with global team with good oral in English on daily basis

-Strong self-motivation

-Be open minded, passion and strong drive

-Excellent team work is required.

We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you. Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.

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