DFT manager
顺卓微电子(西安)有限公司
- 公司规模:50-150人
- 公司性质:外资(欧美)
- 公司行业:电子技术/半导体/集成电路
职位信息
- 发布日期:2017-07-08
- 工作地点:西安-雁塔区
- 招聘人数:若干人
- 工作经验:10年以上经验
- 学历要求:专业培训
- 职位月薪:2.3-3.1万/月
- 职位类别:集成电路IC设计/应用工程师 IC验证工程师
职位描述
职位描述:
Job description:
Define both chip level and block level design-for-test structure and methodology, give out the test plan and align this with Design Team and Testing Team
Implement DFT features including SCAN, Boundary SCAN, MBIST, Analog Macro test logic and etc.
Generate ATPG vectors, at-speed ATPG implementation, assisting with ATPG debug, and ATE test for Yield Diagnosis and Learning process, set the criteria on Memory Redundancy/Replacement
Responsible for scan pattern simulation based on timing files and gate-level netlist, Generate DFT related timing constraints and work with PD team for timing closure; Assist backend engineer with scan chain insertion and timing analysis
Hierarchical AC/DC MBIST and hierarchical AC/DC SCAN design experience in 16nm would be a plus
Work closely with design engineer for design optimization for test coverage improvement, test volume and test time reduction
Work closely with Product Engineer to debug and solve scan pattern failures on tester
Lead and develop Sondrel DFT China Team, develop the local customers in DFT
Qualification:
Bachelors or Master Degree or University Degree or equivalent from Electronic, Electrical or Computer Science.
Logical thinking and sensitive to the problem with good self-study and problem shooting ability; Good communication capability and teamwork spirit.
Team leading experience on DFT
Good language skill in English
Have knowledge about EDA tool as well as VLSI design flow.
Good knowledge in Verilog, VHDL and script language.
Have used Unix/Linux system and EDA tool from Synopsis, Mentor digital and/or analog developing
举报
分享
Job description:
Define both chip level and block level design-for-test structure and methodology, give out the test plan and align this with Design Team and Testing Team
Implement DFT features including SCAN, Boundary SCAN, MBIST, Analog Macro test logic and etc.
Generate ATPG vectors, at-speed ATPG implementation, assisting with ATPG debug, and ATE test for Yield Diagnosis and Learning process, set the criteria on Memory Redundancy/Replacement
Responsible for scan pattern simulation based on timing files and gate-level netlist, Generate DFT related timing constraints and work with PD team for timing closure; Assist backend engineer with scan chain insertion and timing analysis
Hierarchical AC/DC MBIST and hierarchical AC/DC SCAN design experience in 16nm would be a plus
Work closely with design engineer for design optimization for test coverage improvement, test volume and test time reduction
Work closely with Product Engineer to debug and solve scan pattern failures on tester
Lead and develop Sondrel DFT China Team, develop the local customers in DFT
Qualification:
Bachelors or Master Degree or University Degree or equivalent from Electronic, Electrical or Computer Science.
Logical thinking and sensitive to the problem with good self-study and problem shooting ability; Good communication capability and teamwork spirit.
Team leading experience on DFT
Good language skill in English
Have knowledge about EDA tool as well as VLSI design flow.
Good knowledge in Verilog, VHDL and script language.
Have used Unix/Linux system and EDA tool from Synopsis, Mentor digital and/or analog developing
职能类别: 集成电路IC设计/应用工程师 IC验证工程师
公司介绍
Sondrel is a unique and trusted provider of high quality IC designs across multiple end markets. We offer our clients a turnkey service from system to silicon supply. Our designs have appeared in hundreds of leading-edge products including those of the market leaders in mobile phones, cameras, security systems, AR/VR systems, many more.
Founded in 2002 by CEO Graham Curren as a specialist IC design consultancy, today Sondrel provides both design consultancy and an end-to-end silicon solution from architecture and design through production and supply chain to the delivery of fully packaged and tested chips.
Operating from our design centres in UK, France, Morocco, China and India, with sales offices in Israel and the USA, our clients engage with us to create power efficient, highly performant products. Our success is based on delivering on our clients' requirements using our knowledge of how to get the most out of silicon and get it to market reliably, on time and at the right price.
Sondrel是一家为多个终端市场提供高质量的集成电路设计的供应商。我们为客户提供从系统到芯片的一站式服务。我们的设计已经出现在上百种前沿产品中,包括:手机、相机、安全系统、AR及VR等。
Sondrel作为一家集成电路设计咨询公司,于2002年由首席执行官Graham Curren创立。目前Sondrel提供设计咨询及端到端的芯片解决方案,即从架构设计到生产供应链,再到完整的封装测试的交付。
我们在英国、法国、摩洛哥、中国和印度都设有研发中心,在以色列和美国设有销售办事处,与客户合作,创造高效节能及高性能的产品。我们的成功基于满足客户的需求,及如何利用我们的知识***限度的利用芯片,使其可靠地、及时地、以正确的价格投放市场。
Founded in 2002 by CEO Graham Curren as a specialist IC design consultancy, today Sondrel provides both design consultancy and an end-to-end silicon solution from architecture and design through production and supply chain to the delivery of fully packaged and tested chips.
Operating from our design centres in UK, France, Morocco, China and India, with sales offices in Israel and the USA, our clients engage with us to create power efficient, highly performant products. Our success is based on delivering on our clients' requirements using our knowledge of how to get the most out of silicon and get it to market reliably, on time and at the right price.
Sondrel是一家为多个终端市场提供高质量的集成电路设计的供应商。我们为客户提供从系统到芯片的一站式服务。我们的设计已经出现在上百种前沿产品中,包括:手机、相机、安全系统、AR及VR等。
Sondrel作为一家集成电路设计咨询公司,于2002年由首席执行官Graham Curren创立。目前Sondrel提供设计咨询及端到端的芯片解决方案,即从架构设计到生产供应链,再到完整的封装测试的交付。
我们在英国、法国、摩洛哥、中国和印度都设有研发中心,在以色列和美国设有销售办事处,与客户合作,创造高效节能及高性能的产品。我们的成功基于满足客户的需求,及如何利用我们的知识***限度的利用芯片,使其可靠地、及时地、以正确的价格投放市场。
联系方式
- Email:wendy.ren@nottingham.edu.cn
- 公司地址:地址:span西安市二环南路西段64号凯德广场写字楼2303-2304室