北京招聘

职位描述：
Job Description
Description
Work closely with frontend and backend design teams, as well as test engineers. Participate in logic design for some timing critical blocks in SOHO switch/PHY chips and ASICs. Perform logic synthesis, floor planning, timing analysis and timing signoff for chip tapeout. Work on DFT designs including MBIST, EDT, OCC, JTAG. Run Mentor and Synopsys tools to create and verify ATPG patterns. Work with test engineers to build up and debug test programs.
Qualifications
? MSEE degree
? 2~4 years of hand-on experience in digital design, running EDA tools of simulation, synthesis, timing analysis, formal verification, DFT and ATPG
? Solid knowledge and background in ASIC development
? Good communication skills 举报 分享

We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you. Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.

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