北京招聘

ASIC Implementation Engineer (PHS)
Job Description:
- Block, IP macro or SoC level implementation in 28nm or 20nm TSMC/UMC process
- UPF Synthesis with Synopsys DC or DCT/G flows
- RTL2Gate and Gate2Gate formal check with LEC and/or formality tools.
- Working with BE team to timing closure in Primetime-SI on multi-corners and multi-modes
- Ability to build or perfect the EDA-methodology-flow with perl, tcl or shell
- Knowledge on DFT (mbist/scan) will be an added advantage

Qualifications:
- BSEE degree or above
- Strong understanding of synthesis flow using DC/DCT/DCG - for a low power (UPF) and
high speed- complex SoC
- Hands on experience with formal verification tools such as LEC and/or formality
- Must have the CTS conceptions in ICC at P&R stage
- Strong STA skills. Must have thorough knowledge on closing timing at unit and top level
- Experience in mbist and scan will be plus
- Proficient in Perl, Tcl and Shell programming
-Good team work spirit

please send your resume to jiangrr@marvell.com

We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you. Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.

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