北京招聘

Job Title: Senior ASIC Design Engineer

Description:
1. Responsible for data interface IP/SoC mid-end flow including formal check, synthesis and STA check.
2. Implement DFT structures (internal scan, JTAG, MBIST) in SoC Design.
3. Interface with back-end design team.
4. Design and develop next-gen high-performance and low power interface IP core (e.g. PCIe, USB) and SoC using in storage and cell phones.
5. Participate in IP module design and SOC top integration.

Qualifications:
1. MSEE with 2+ years
2. Proficiency in logic design, simulation, synthesis.
3. Power user of EDA tools including Sypglass, DC, PT, ICC/Encounter, etc.
4. Experience in DFT design
5. Proficiency in Perl, TCL and Makefile script
6. Knowledge of IP usage and SOC architecture

We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you. Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.

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