北京招聘

Job Title: ASIC DFT design Engineer
Location: Shanghai

Job Description:
-Block, IP and SoC level DFT implementation (JTAG, Scan, Mbist and analog/IP test etc.) and RTL integration;
-Participate in test spec/plan definition; create the DFT design document and signoff DFT review checklists;
-Test patterns/vectors generation and verification;
-Interface to backend team on physical design and timing closure;
-Interface to test engineers on ATE and vectors bring-up and debugging;
-Chip DFT quality sign-off
-DFT STA, constraint generation, formal and timing closure

Qualifications:
- DFT design and integration experience
- Hands on DFT implementation experience (Bscan, Mbist, DC/AC Scan, analog IP test circuit integration, IDDQ test, ATPG and test pattern verification)
- Expertise with DFT tools from Synopsy, Mentor, Syntest etc.
- Strong logic design and verification background
- Experience in Synthesis and STA will be plus
- Proficient in Perl, tcl and shell programming
- BSEE degree or above
- Good team work spirit

please send your resume to jiangrr@marvell.com

We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you. Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.

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