北京招聘

Job Descriptions:
In this role you will work with algorithm designer, participate in designing and implementing block-level and system-level modules for digital signal processing IC.
Responsibilities include micro-architecture definition, logic design, DFT, timing closure, verification and FPGA prototyping.

Qualifications:
1. MS degree in Electrical Engineering or Computer Science
2. 1+ years experience in micro-architecture and RTL logic design (Verilog and/or VHDL).
3. Good understanding of digital signal processing theory, or well known soc design.
4. Familiar with DC , DFT, FORMALITY , STA, ATPG, BIST and power analysis.
7. Has ability of independent debugging and self-learning.
5. Experience in FPGA-based prototyping verification is a plus.
6. Familiar with perl, makfile, tcl is a plus.
8. Excellent communication and presentation skills
9. Team player, and easy to work with

       北京芯动联科微电子技术有限公司是专注于MEMS传感器产品的开发设计及应用，以敏感结构的研发为基础，配以专用ASIC的应用，给客户提供一站式总体解决方案的新技术企业。

    我公司致力于打造国内一流、有重大影响力和竞争力的集成电路研发和生产基地。专注于MEMS陀螺仪产品研发、以MEMS及其ASIC的设计技术为核心竞争力、以替代进口产品为主，参与国际竞争、突破西方国家技术封锁、服务于国民经济。坚持自主创新，以推动国家战略性关键新兴产业为己任。

    芯动联科由海外专家技术团队营运，在已有的雄厚技术储备和产业实践基础上兼收世界领先科技。组建了一支拥有国际前沿技术、专注于MEMS产品开发的研发，生产，市场营销的精英团队。公司目前处于业务发展阶段，亟待界内优秀人才加入。
   
     我们怀揣着共同的理想，我们勤奋守正、热爱学习，我们在一个尊重、信任的环境中成长，我们选的是人而非职位，若你与我们思想对接，欢迎你来！