北京 [切换城市] 北京招聘北京电子/电器/半导体/仪器仪表招聘北京集成电路IC设计/应用工程师招聘

Synopsys Digital IP Engineer_SERDES PCIe SATA USB

新思科技(上海)有限公司

  • 公司规模:500-1000人
  • 公司性质:外资(欧美)
  • 公司行业:电子技术/半导体/集成电路

职位信息

  • 发布日期:2014-05-22
  • 工作地点:武汉
  • 招聘人数:若干
  • 工作经验:三年以上
  • 学历要求:本科
  • 语言要求:英语良好
  • 职位月薪:面议
  • 职位类别:集成电路IC设计/应用工程师  IC验证工程师

职位描述

Job Description and Requirements

Seeking a highly motivated and innovative digital design and verification engineer with strong theoretical and practical background in high-speed data recovery circuits. Working as part of a highly experienced mixed-signal design team, the candidate will be involved in designing and maintaining current and next generation PCIe, SATA, 10G-KR and USB 2/3 SERDES products. The position offers excellent opportunity to work with an expert team of digital and mixed signal designers responsible for delivering high-end mixed-signal designs from specification development to performing functional and performance tests on the test-chips. In addition, this is a great opportunity to work with a wide suite of in-house digital design and verification tools, including VCS, Design Compiler, PrimeTime, LEDA.



Job Responsibilities:

- Architecture and RTL coding of high-speed digital circuits, modeling of analog blocks.

- Writing verilog and system-verilog test-benches. Performing functional coverage, assertion coverage, and code coverage.

- Defining place and route constraints, resolving STA issues and performing gate-level simulations.

- Defining and debugging DFT structures in the designs for high DFT coverage.

- Managing, reviewing, and tracking the design and verification tasks executed by teams at off-site locations

- Interacting with customer support and back-end design teams.

- Ability to lead and manage small team of engineers



This position typically requires BS or MS plus at least 2-4 years of digital design and verification experience in the industry as well as hands on experience in designing high-speed digital circuits, writing complex test-cases in Verilog and System Verilog, and familiarity with code quality metrics. Candidates must have a deep understanding of asynchronous clock crossings, DFT design methodologies, and synthesis implications of RTL. Knowledge of back-end synthesis tools DC/PT is a plus as are good organization and communication skills for interacting between different design groups and customer support teams.

公司介绍

Synopsys公司(Nasdaq:SNPS)是为全球集成电路设计提供电子设计自动化(EDA)软件工具的企业。为全球电子市场提供先进的IC设计与验证平台,致力于复杂的芯片上系统(SoCs)的开发。同时,Synopsys公司还提供知识产权和设计服务,为客户简化设计过程,提高产品上市速度。新思公司总部设在美国加州硅谷,有超过60家分公司分布在北美、欧洲、日本与亚洲。
Synopsys,Inc.[Nasdaq:SNPS],headquartered in Mountain View,California,creates leading electronic design automation(EDA)tools for the global electronics market.The company delivers advanced design technologies and solutions to developers of complex integrated circuits,electronic systems and systems on a chip.Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers.
Over the past several years,Synopsys has entered into partnerships with IBM,SGS-Thomson,SEMATEC,Toshiba and others to develop tools and design flows for complex IC and ASIC designs at 0.25 micron and below.The Company has also partnered with programmable logic vendors and other EDA companies to tackle issues ranging from the impact of complex silicon in programmable devices to sound design reuse strategies.

You'd better submit your resume via jobs-china@synopsys.com.

联系方式

  • 公司网站:http://www.synopsys.com
  • Email:jobs-china@synopsys.com.Job
  • 公司地址:上海市长宁路1027号,兆丰广场14-16楼
  • 邮政编码:200050
  • 联系人:Synopsys Recruiter