Synopsys ASIC Design/Verfication Engineer_DDR PHY
新思科技(上海)有限公司
- 公司规模:500-1000人
- 公司性质:外资(欧美)
- 公司行业:电子技术/半导体/集成电路
职位信息
- 发布日期:2014-05-22
- 工作地点:武汉
- 招聘人数:若干
- 工作经验:三年以上
- 语言要求:英语良好
- 职位月薪:面议
- 职位类别:集成电路IC设计/应用工程师 IC验证工程师
职位描述
The ideal candidate will have good background in RTL design and directed verification. Design expertise includes understanding Standard Specifications/micro-architecture documents, ability to design for low area/power; Designer should have understanding of good coding guidelines. Directed Verification expertise includes knowledge of verification concepts, definition of verilog testbench, test case development and verifying the design under test. Also the candidate should be able to analyze the coverage metrics and improve them with definition of additional test cases.
Job responsibilities include understanding DDR memory system and working on the design/directed verification of DDR design. Be able to implement test benches and test cases in HDL like Verilog is needed. The candidate will work in a project and team oriented environment with teams spread across multiple sites worldwide.
Have BSEE in EE with 3+ years of relevant experience or MS with 1+ years of relevant experience in one or more of the following areas:
-Hands on experience with Verilog coding and Simulation tools
-Prior ASIC/IP directed verification skills with essential knowledge of Verilog/ System Verilog
-Synthesis flow and static timing flows, Formal checking, etc is a plus
-Knowledge of DDR memory system is a plus
-Knowledge of C/C++/System C is a plus
-Experience with Perl/Shell/Makefile scripts is a plus.
In addition, the candidate will have good communication skills, will be a team player and will have good problem solving skills.
The candidate will be part of the Solutions Group at our Wuhan Design Center, China. The position offers learning and growth opportunities in Synopsys' new Design Center at Wuhan.
Job responsibilities include understanding DDR memory system and working on the design/directed verification of DDR design. Be able to implement test benches and test cases in HDL like Verilog is needed. The candidate will work in a project and team oriented environment with teams spread across multiple sites worldwide.
Have BSEE in EE with 3+ years of relevant experience or MS with 1+ years of relevant experience in one or more of the following areas:
-Hands on experience with Verilog coding and Simulation tools
-Prior ASIC/IP directed verification skills with essential knowledge of Verilog/ System Verilog
-Synthesis flow and static timing flows, Formal checking, etc is a plus
-Knowledge of DDR memory system is a plus
-Knowledge of C/C++/System C is a plus
-Experience with Perl/Shell/Makefile scripts is a plus.
In addition, the candidate will have good communication skills, will be a team player and will have good problem solving skills.
The candidate will be part of the Solutions Group at our Wuhan Design Center, China. The position offers learning and growth opportunities in Synopsys' new Design Center at Wuhan.
公司介绍
Synopsys公司(Nasdaq:SNPS)是为全球集成电路设计提供电子设计自动化(EDA)软件工具的企业。为全球电子市场提供先进的IC设计与验证平台,致力于复杂的芯片上系统(SoCs)的开发。同时,Synopsys公司还提供知识产权和设计服务,为客户简化设计过程,提高产品上市速度。新思公司总部设在美国加州硅谷,有超过60家分公司分布在北美、欧洲、日本与亚洲。
Synopsys,Inc.[Nasdaq:SNPS],headquartered in Mountain View,California,creates leading electronic design automation(EDA)tools for the global electronics market.The company delivers advanced design technologies and solutions to developers of complex integrated circuits,electronic systems and systems on a chip.Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers.
Over the past several years,Synopsys has entered into partnerships with IBM,SGS-Thomson,SEMATEC,Toshiba and others to develop tools and design flows for complex IC and ASIC designs at 0.25 micron and below.The Company has also partnered with programmable logic vendors and other EDA companies to tackle issues ranging from the impact of complex silicon in programmable devices to sound design reuse strategies.
You'd better submit your resume via jobs-china@synopsys.com.
Synopsys,Inc.[Nasdaq:SNPS],headquartered in Mountain View,California,creates leading electronic design automation(EDA)tools for the global electronics market.The company delivers advanced design technologies and solutions to developers of complex integrated circuits,electronic systems and systems on a chip.Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers.
Over the past several years,Synopsys has entered into partnerships with IBM,SGS-Thomson,SEMATEC,Toshiba and others to develop tools and design flows for complex IC and ASIC designs at 0.25 micron and below.The Company has also partnered with programmable logic vendors and other EDA companies to tackle issues ranging from the impact of complex silicon in programmable devices to sound design reuse strategies.
You'd better submit your resume via jobs-china@synopsys.com.
联系方式
- 公司网站:http://www.synopsys.com
- Email:jobs-china@synopsys.com.Job
- 公司地址:上海市长宁路1027号,兆丰广场14-16楼
- 邮政编码:200050
- 联系人:Synopsys Recruiter