北京 [切换城市] 北京招聘北京电子/电器/半导体/仪器仪表招聘北京集成电路IC设计/应用工程师招聘

Synopsys Emulation/Verification AC (FPGA Base)

新思科技(上海)有限公司

  • 公司规模:500-1000人
  • 公司性质:外资(欧美)
  • 公司行业:电子技术/半导体/集成电路

职位信息

  • 发布日期:2014-04-29
  • 工作地点:深圳
  • 招聘人数:1
  • 工作经验:三年以上
  • 学历要求:硕士
  • 语言要求:英语熟练
  • 职位月薪:面议
  • 职位类别:集成电路IC设计/应用工程师  

职位描述

JD:
Verification is the number one bottleneck in SOC designs today. Synopsys is uniquely positioned to offer the most complete verification solution in market today. VCS is the simulation platform for Synopsys verification flow, it incorporates a suite of built-in high performance next generation technologies for test bench automation, assertion based verification, coverage closure, etc., which are needed for verifying challenging multi-million gate designs. ZeBu is the emulation platform for Synopsys verification flow, it’s the industry’s performance & capacity leader in Emulation.

As a Senior CAE for Verification, based in Shanghai, candidate will be responsible for successful deployment of Synopsys verification flow to a growing customer base in AsiaPacific. The CAE responsibilities include onsite deployment of industry leading automation and verification technologies, creation of technical collateral, defining new methodology, and product support, testing and writing specifications for enhancement. Candidate will be responsible to interact with and support customers, sales, and marketing, and help analyze and resolve complex verification issues for customers’ cutting edge ASIC designs. The position offers a great opportunity to grow by learning state-of-art verification flows from Synopsys.

Requirements:
MS or PhD majored in EE with more than 5 years of IC design/verification/emulation experiences. Good knowledge of high-level design methodologies and strong communication skills are required. Ability to work with customers and R&D teams is important. Real project experience in ASIC/SoC emulation and good expertise on popular emulators like Palladium/Veloce/Zebu are required. Proficient with HDL (Verilog/VHDL), HVL(e/vera/systemverilog), C/C++, Unix, and having a strong understanding of ASIC design flows, VLSI, and/or CAD-engineering. Experience on VMM/OVM/UVM and knowledge of simulator-emulator co-emulation are preferred.

公司介绍

Synopsys公司(Nasdaq:SNPS)是为全球集成电路设计提供电子设计自动化(EDA)软件工具的企业。为全球电子市场提供先进的IC设计与验证平台,致力于复杂的芯片上系统(SoCs)的开发。同时,Synopsys公司还提供知识产权和设计服务,为客户简化设计过程,提高产品上市速度。新思公司总部设在美国加州硅谷,有超过60家分公司分布在北美、欧洲、日本与亚洲。
Synopsys,Inc.[Nasdaq:SNPS],headquartered in Mountain View,California,creates leading electronic design automation(EDA)tools for the global electronics market.The company delivers advanced design technologies and solutions to developers of complex integrated circuits,electronic systems and systems on a chip.Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers.
Over the past several years,Synopsys has entered into partnerships with IBM,SGS-Thomson,SEMATEC,Toshiba and others to develop tools and design flows for complex IC and ASIC designs at 0.25 micron and below.The Company has also partnered with programmable logic vendors and other EDA companies to tackle issues ranging from the impact of complex silicon in programmable devices to sound design reuse strategies.

You'd better submit your resume via jobs-china@synopsys.com.

联系方式

  • 公司网站:http://www.synopsys.com
  • Email:jobs-china@synopsys.com.Job
  • 公司地址:上海市长宁路1027号,兆丰广场14-16楼
  • 邮政编码:200050
  • 联系人:Synopsys Recruiter