Backend Design Methodologist
飞思卡尔半导体(中国)有限公司上海分公司
- 公司性质：外资(欧美)
- 公司行业：电子技术/半导体/集成电路
职位信息
- 发布日期：2013-10-15
- 工作地点：苏州
- 招聘人数：若干
- 职位类别：集成电路IC设计/应用工程师
职位描述
Freescale Semiconductor is the global leader in embedded processing solutions, supporting the automotive, consumer, industrial and networking markets. From microprocessors and microcontrollers to sensors, analog ICs and connectivity — our vital technologies are the foundation to the innovations that make our world greener, safer, healthier and more connected. For more than 50 years, Freescale has played an essential role in the evolution of embedded solutions, and we want you to be a part of our next half-century. Freescale is committed to attracting great people of all styles, thoughts, cultures and backgrounds. We are driven by a culture of ownership, teamwork, and results — an engagement worldwide of more than 20,000 employees.
Job
? Flow and Methodology team participates in global design flow and methodology development and deployment in SOC designs.
? Responsible for Freescale design flow and methodology development.
? Major on physical design flow and methodology development including advanced design technology development
? Responsible for Die size reduction methodology, low power methodology and floorplan.
? Responsible for chip-finishing, DFM methodology devlopment.
? Responsible for IC design flow development and work with the global flow and methodology team to do new technology flow and methodology development.
Qualifications (physical build)- External
? BSEE or high required.
? Engineering with 2-5 or more years experience in rtl2gate synthesis, timing closure.
? Relevant project experience rtl2gate synthesis, timing closure … soc physical implementation activities.
? Experience using backend EDA tools; i.e. Cadence EDI, ETS, EPS, virtuoso…., Calibre physical verification tools, etc.
? Relevant technology experience from 250nm to 28nm.
? Software development experience is a big plus..
? Good grasp of C/C++, Perl/TCL, and skill scripts in Linux/Unix environment.
.
Backend Design methodologist:
Responsibilities:
- Responsible for IC backend designs and working with the global design team to do complex SOC physical implementation for deep submicron design.
- Logic/physical synthesis.
- Die size estimation, floor-planning, power planning and analysis.
- Clock tree synthesis, place and routing.
- Static timing, cross-talk analysis until reaching final timing and SI closure.
- DFM; working for design for manufacture.
- Layout integration, DRC/LVS and final GDS tape out.
Requirements:
- Bachelor, Master on Electronic/Microelectronics Engineering and Computer Science.
- Experience in IC backend design.
- Experience with EDA backend tools.
- Familiar with Perl/TCL scripts in Linux/Unix environment is a plus.
- Hands-on experience on doing millions gates of design on submicron, like 0.13um, 90nm or below is a big plus.
- Good written and oral English communication skills.
- Good team work spirit, easy to cooperate with team members.
Job
? Flow and Methodology team participates in global design flow and methodology development and deployment in SOC designs.
? Responsible for Freescale design flow and methodology development.
? Major on physical design flow and methodology development including advanced design technology development
? Responsible for Die size reduction methodology, low power methodology and floorplan.
? Responsible for chip-finishing, DFM methodology devlopment.
? Responsible for IC design flow development and work with the global flow and methodology team to do new technology flow and methodology development.
Qualifications (physical build)- External
? BSEE or high required.
? Engineering with 2-5 or more years experience in rtl2gate synthesis, timing closure.
? Relevant project experience rtl2gate synthesis, timing closure … soc physical implementation activities.
? Experience using backend EDA tools; i.e. Cadence EDI, ETS, EPS, virtuoso…., Calibre physical verification tools, etc.
? Relevant technology experience from 250nm to 28nm.
? Software development experience is a big plus..
? Good grasp of C/C++, Perl/TCL, and skill scripts in Linux/Unix environment.
.
Backend Design methodologist:
Responsibilities:
- Responsible for IC backend designs and working with the global design team to do complex SOC physical implementation for deep submicron design.
- Logic/physical synthesis.
- Die size estimation, floor-planning, power planning and analysis.
- Clock tree synthesis, place and routing.
- Static timing, cross-talk analysis until reaching final timing and SI closure.
- DFM; working for design for manufacture.
- Layout integration, DRC/LVS and final GDS tape out.
Requirements:
- Bachelor, Master on Electronic/Microelectronics Engineering and Computer Science.
- Experience in IC backend design.
- Experience with EDA backend tools.
- Familiar with Perl/TCL scripts in Linux/Unix environment is a plus.
- Hands-on experience on doing millions gates of design on submicron, like 0.13um, 90nm or below is a big plus.
- Good written and oral English communication skills.
- Good team work spirit, easy to cooperate with team members.
公司介绍
恩智浦半导体（纳斯达克代码：NXPI）致力于通过先进的安全连结及基础设施解决方案为人们更智慧安全、轻松便捷的生活保驾护航。作为全球领先的嵌入式应用安全连接解决方案领导者，恩智浦不断推动着互联汽车、端对端安全及隐私、智能互联解决方案市场的创新。恩智浦拥有超过60年的专业技术及经验，拥有29,000名员工，业务遍及30多个国家，2019年的营业额达88.8亿美元。