Validation Engineer
飞思卡尔半导体(中国)有限公司上海分公司
- 公司性质：外资(欧美)
- 公司行业：电子技术/半导体/集成电路
职位信息
- 发布日期：2013-10-15
- 工作地点：苏州
- 招聘人数：若干
- 工作经验：三年以上
- 学历要求：本科
- 职位类别：IC验证工程师
职位描述
Freescale is seeking an individual to work as part of validation team to co-work with ASIC designer to define FPGA validation plan and propose FPGA partition and redesign with ASIC design team and SW team. The ideal candidate shall be a team player who can communicate at all levels. In addition, this individual shall be capable of defining requirements and creating test case for pre/post silicon validation.
Responsibities
? To define the FPGA development plan according to the requirement from design or software team
? Porting internal ASIC design to FPGA platform
? To setup FPGA simulation environment
? To mentor junior validation engineer in FPGA development
? To define pre-silicon or post-silicon validation test plan and do resource estimation
? To create and execute validation test for both pre-silicon and post-silicon validation
? To report validation result to management team
Qualifications
? BS/MS in electrical/computer engineering with 3+ years of experience in FPGA development
? Familiar with Xilinx device structure & synplicity tools (synplify_premier, identify, certify) & Xilinx PAR tools
? Experienced in FPGA design & simulation environment setup
? Good understand on the FPGA timing, FPGA clocking
? Must be proficient in Verilog HDL
? Familiar with logic simulators and debug tools (VCS, NCSIM, Verdi and etc.)
? Working knowledge in C/C++, Makefile
? Big plus with experience in USB 2.0 or Ethernet
? Big plus with experience in ARM M0, M0+ and M4 based MCU
? Big plus with experience in IAR and CodeWarrior debugger Tool
? Fluent English (both written and spoken) and excellent communication skills. Ability to write professional and technical reports and procedures.
Responsibities
? To define the FPGA development plan according to the requirement from design or software team
? Porting internal ASIC design to FPGA platform
? To setup FPGA simulation environment
? To mentor junior validation engineer in FPGA development
? To define pre-silicon or post-silicon validation test plan and do resource estimation
? To create and execute validation test for both pre-silicon and post-silicon validation
? To report validation result to management team
Qualifications
? BS/MS in electrical/computer engineering with 3+ years of experience in FPGA development
? Familiar with Xilinx device structure & synplicity tools (synplify_premier, identify, certify) & Xilinx PAR tools
? Experienced in FPGA design & simulation environment setup
? Good understand on the FPGA timing, FPGA clocking
? Must be proficient in Verilog HDL
? Familiar with logic simulators and debug tools (VCS, NCSIM, Verdi and etc.)
? Working knowledge in C/C++, Makefile
? Big plus with experience in USB 2.0 or Ethernet
? Big plus with experience in ARM M0, M0+ and M4 based MCU
? Big plus with experience in IAR and CodeWarrior debugger Tool
? Fluent English (both written and spoken) and excellent communication skills. Ability to write professional and technical reports and procedures.
公司介绍
恩智浦半导体（纳斯达克代码：NXPI）致力于通过先进的安全连结及基础设施解决方案为人们更智慧安全、轻松便捷的生活保驾护航。作为全球领先的嵌入式应用安全连接解决方案领导者，恩智浦不断推动着互联汽车、端对端安全及隐私、智能互联解决方案市场的创新。恩智浦拥有超过60年的专业技术及经验，拥有29,000名员工，业务遍及30多个国家，2019年的营业额达88.8亿美元。