北京招聘

Design For Test (DFT) Engineer

Responsibilities:

• Participate in definition and driving both chip level and block level design-for-test structure and methodology for SOC designs.
• Responsible for Automatic Test Pattern Generation and model creation, memory Built In Self Test, Embedded Deterministic Test and Boundary scan test.
• Work closely with design engineer for design optimization for test coverage improvement, test volume and test time reduction.
• Responsible for scan pattern simulation based on timing files and gate-level netlist, assist backend engineer with scan chain insertion and timing analysis.
• Work closely with product and test engineers to debug and solve scan pattern failures in tester.
• Work as a global team to do complex SOC design and test.

Qualifications

• MSEE required
• Engineering with 2+ years IC design/verification experience
• Experience in Design for Test (DFT) is a strong plus
• Relevant project experience in digital designs based on verilog or VHDL, with basic knowledge of design flow, including RTL coding, verification, synthesis, STA, test and validation.
• Relevant project experience in design for test activities, experience using tools including: Fastscan, TestKompress, MBIST architect, YieldAssist etc.
• Familiar with main EDA tools, such as Cadence, Mentor, and Synposis.
• Good grasp of Verilog/VHDL, C/C++ and Perl/TCL scripts in Linux/Unix environment.
• Familiar with ATE platform, software and hardware is a plus.
• Good English communication skills

恩智浦半导体（纳斯达克代码：NXPI）致力于通过先进的安全连结及基础设施解决方案为人们更智慧安全、轻松便捷的生活保驾护航。作为全球领先的嵌入式应用安全连接解决方案领导者，恩智浦不断推动着互联汽车、端对端安全及隐私、智能互联解决方案市场的创新。恩智浦拥有超过60年的专业技术及经验，拥有29,000名员工，业务遍及30多个国家，2019年的营业额达88.8亿美元。