北京招聘

Senior verification Engineer
Responsibilities:
Responsibilities will include developing verification environment; developing test plans for and verifying the function of ASIC; hands-on implementation work for every aspect of ASIC verification, working closely with the system group, architects, design and verification teams. The successful candidate should have experience going through at least one complete and successful ASIC design/verification cycle from architecting and creating ASIC test environment to full completion of the verification work. The candidate also needs to have a full understanding of design using Verilog and working experience with SystemVerilog. A strong communication skill in both Chinese and English is required.
Qualifications:
5+ years of ASIC Design verification experience, complex SOC verification experience is preferred
Strong programming skills in SystemVerilog
Knowledgeable in Verilog/Verilog-PLI/SystemC/SVA/C/C++
Working Experience with UVM/OVM/VMM (at least one of them)
Responsible for implementation of verification environment and generation of high quality test cases.
BS/MS EE, CE or CS

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