MTS - IC design engineering
超威半导体(中国)有限公司
- 公司规模:1000-5000人
- 公司性质:外资(欧美)
- 公司行业:电子技术/半导体/集成电路
职位信息
- 发布日期:2014-05-28
- 工作地点:北京
- 招聘人数:若干
- 工作经验:五年以上
- 学历要求:本科
- 语言要求:英语熟练
- 职位类别:集成电路IC设计/应用工程师 半导体技术
职位描述
Requirements:
The candidate is preferred to be MSEE with minimum of 6 years, or BSEE with minimum of 8 years experience in digital ASIC/SOC design engineering.
The candidate should have deep understanding on ASIC/SOC design flow and must be proficient in quite a lot of following skill sets:
1. RTL(verilog) coding and style checking
2. scripts based on makefile, perl, TCL or csh/tcsh
3. clock-domain-cross checking
4. dynamic logic simulation or post-layout simulation
5. logic synthesis or physical Synthesis
6. static timing analysis
7. logic equivalency checking
8. ECO(engineering change order)
9. top level integration, floor planning, pad-ring design
10. clock distribution
11. design for test, design for debug or design for power
It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, , driving execution of quality and timely result, capability to solve complex, novel and no-recurring problems and decision-making on critical technical areas
Hands-on lab experience is another plus, able to understand and/or use the use scopes, logic analyzers, has knowledge or skill of board-level lab debugging.
Responsibility:
The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include technical leading on the following tasks from time to time: specification, top level SOC design tasks, HDL coding, synthesis, timing closure, etc. The job may require some lab bring up and debugging of the reference board system after the tape-out chip comes back.
The candidate is preferred to be MSEE with minimum of 6 years, or BSEE with minimum of 8 years experience in digital ASIC/SOC design engineering.
The candidate should have deep understanding on ASIC/SOC design flow and must be proficient in quite a lot of following skill sets:
1. RTL(verilog) coding and style checking
2. scripts based on makefile, perl, TCL or csh/tcsh
3. clock-domain-cross checking
4. dynamic logic simulation or post-layout simulation
5. logic synthesis or physical Synthesis
6. static timing analysis
7. logic equivalency checking
8. ECO(engineering change order)
9. top level integration, floor planning, pad-ring design
10. clock distribution
11. design for test, design for debug or design for power
It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, , driving execution of quality and timely result, capability to solve complex, novel and no-recurring problems and decision-making on critical technical areas
Hands-on lab experience is another plus, able to understand and/or use the use scopes, logic analyzers, has knowledge or skill of board-level lab debugging.
Responsibility:
The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include technical leading on the following tasks from time to time: specification, top level SOC design tasks, HDL coding, synthesis, timing closure, etc. The job may require some lab bring up and debugging of the reference board system after the tape-out chip comes back.
公司介绍
AMD公司成立于1969年,总部位于美国加利福尼亚州桑尼维尔。AMD(NYSE: AMD)是一家创新的科技公司,致力于与客户及合作伙伴紧密合作,开发下一代面向商用、家用和游戏领域的计算和图形处理解决方案。AMD的业务遍布全球,拥有约为12000名员工。
联系方式
- Email:bella.yu@amd.com
- 公司地址:上海-浦东新区 张江 环科路669号凯瑞大厦