CIC engineers principal staff
Cypress Semiconductor Technology (Shanghai) Co., Ltd塞普锐思半导体技术（上海）有限公司
- 公司规模：150-500人
- 公司性质：外资(欧美)
- 公司行业：电子技术/半导体/集成电路
职位信息
- 发布日期：2012-07-31
- 工作地点：上海-浦东新区
- 招聘人数：1
- 工作经验：五年以上
- 学历要求：本科
- 语言要求：英语熟练
- 职位类别：集成电路IC设计/应用工程师 半导体技术
职位描述
Principal level:
Job description:
This is a position for a principal or above chip integration physical design engineer.
The responsibilities of this position are:
- RTL to GDS tech lead, and project schedule/plan
- Hands on work covering synthesis, DFT, LEC, low power verification (MVRC)
- Floorplan, P&R
- STA including OCV, cross talk and VASTA
- Interacting with IP and RTL designers to solve IP and RTL design issues,
- Improve DFT coverage, and solve constraint/timing issues
- Interacting with EDA tool vendors to solve tools issues
- Strong experience in design flow development and improvement
Job specific requirements:
- Minimum 10 years physical design experience on complexity full chip physical designs at advanced technology nodes
- Demonstrate strong hands on experience in complete full chip RTL to GDS implementations (synthesis, DFT, P&R and sign-off flow)
- Must have strong low power design experience with good transistor level knowledge
- UPF/CPF experience is a plus
- Must have thorough knowledge on STA and cross talk analysis
- Familiar with "make" and strong scripting experience such as Perl and Tcl
- Must be very strong with Synthesis, DFT, P&R and sign-off tools
- Good understanding of RTL coding
- Must have excellent verbal and written communication skill
- BS in Electrical Engineering or related field is required.
Sr Staff level
This is a position for a senior staff chip integration physical design engineer.
The responsibilities of this position are:
- RTL to GDS physical design
- Hands on work covering synthesis, DFT insertion, LEC, low power
- Floorplan, P&R
- STA including OCV and cross talk analysis
- Interacting with design to solve design issue during physical design
- Solve constraint/timing issues
- Interacting with EDA tool vendors to solve tools issues
- Design flow development and improvement
Job Specific Requirements:
- 5-10 years physical design experience on complexity full chip physical designs at advanced technology nodes
- Demonstrate hands on experience in complete full chip RTL to GDS implementations (synthesis, DFT insertion, P&R and sign-off flow)
- Must have good low power design experience in CIC flow
- UPF/CPF experience is a plus
- Must have thorough knowledge on STA and cross talk analysis
- Good scripting experience such as Perl and/or Tcl
- Good experience with Synthesis, DFT, P&R and sign-off tools
- Must have excellent verbal and written communication skill
- BS in Electrical Engineering or related field is required.
Job description:
This is a position for a principal or above chip integration physical design engineer.
The responsibilities of this position are:
- RTL to GDS tech lead, and project schedule/plan
- Hands on work covering synthesis, DFT, LEC, low power verification (MVRC)
- Floorplan, P&R
- STA including OCV, cross talk and VASTA
- Interacting with IP and RTL designers to solve IP and RTL design issues,
- Improve DFT coverage, and solve constraint/timing issues
- Interacting with EDA tool vendors to solve tools issues
- Strong experience in design flow development and improvement
Job specific requirements:
- Minimum 10 years physical design experience on complexity full chip physical designs at advanced technology nodes
- Demonstrate strong hands on experience in complete full chip RTL to GDS implementations (synthesis, DFT, P&R and sign-off flow)
- Must have strong low power design experience with good transistor level knowledge
- UPF/CPF experience is a plus
- Must have thorough knowledge on STA and cross talk analysis
- Familiar with "make" and strong scripting experience such as Perl and Tcl
- Must be very strong with Synthesis, DFT, P&R and sign-off tools
- Good understanding of RTL coding
- Must have excellent verbal and written communication skill
- BS in Electrical Engineering or related field is required.
Sr Staff level
This is a position for a senior staff chip integration physical design engineer.
The responsibilities of this position are:
- RTL to GDS physical design
- Hands on work covering synthesis, DFT insertion, LEC, low power
- Floorplan, P&R
- STA including OCV and cross talk analysis
- Interacting with design to solve design issue during physical design
- Solve constraint/timing issues
- Interacting with EDA tool vendors to solve tools issues
- Design flow development and improvement
Job Specific Requirements:
- 5-10 years physical design experience on complexity full chip physical designs at advanced technology nodes
- Demonstrate hands on experience in complete full chip RTL to GDS implementations (synthesis, DFT insertion, P&R and sign-off flow)
- Must have good low power design experience in CIC flow
- UPF/CPF experience is a plus
- Must have thorough knowledge on STA and cross talk analysis
- Good scripting experience such as Perl and/or Tcl
- Good experience with Synthesis, DFT, P&R and sign-off tools
- Must have excellent verbal and written communication skill
- BS in Electrical Engineering or related field is required.
公司介绍
美国CYPRESS半导体公司
塞普锐思公司总部位于美国硅谷，全球拥有近4000名员工，并于世界各主要城市设有销售中心。公司主要生产PSoC, USB, 存储器，时钟，图像传感器等产品，旨在为全球消费类电子和通讯产品等提供品质优良的芯片和解决方案。目前，塞普锐思公司在可编程SoC，USB（有线和无线），存储器，通讯时钟等产品方面处于行业领先地位。
基于业务的飞速增长和更好的服务于亚太客户，塞普锐思公司正在扩大在中国的研发和服务团队。公司位于张江集电港，包括集成电路设计，方案中心，市场和销售，Fab等。
公司有良好的企业文化，非常注重员工的个人发展，能够提供完善的培训体系，并有出国培训机会。
塞普锐思公司已于纽约股票交易所上市，代号"CY"。
请登录公司网站了解更多信息:http://www.cypress.com
Cypress Semiconductor Co., Ltd delivers high-performance, mixed-signal, programmable solutions that provides customers with rapid time-to-market and exceptional system value. Cypress offerings include the flagship PSoC programmable system-on-chip families and derivatives such as PowerPSoC® solutions for high-voltage and LED lighting applications, CapSense® touch sensing and TrueTouchTM solutions for touchscreens. Cypress is the world leader in USB controllers, including the high-performance West Bridge® solution that enhances connectivity and performance in multimedia handsets. Cypress is also a leader in high-performance memories and programmable timing devices. Cypress serves numerous markets including consumer, mobile handsets, computation, data communications, automotive, industrial.
Based on the rapid business growth and in order to provide better services for its Asian customers, Cypress is now expanding the sales/marketing and research/development teams in China. Cypress China currently consists of IC design, Applications, Sales and marketing, Manufacturing, TE/PE and Finance departments and is located at ZhangJiang Riverfront Harbor.
Cypress has an educational and US-based company culture, employee training plans and salary benefit systems.
Cypress employs nearly 4,000 people worldwide with headquarters located in Silicon Valley. Its shares are listed on the NYSE (CY).
More information about Cypress is available at http://www.cypress.com
塞普锐思公司总部位于美国硅谷，全球拥有近4000名员工，并于世界各主要城市设有销售中心。公司主要生产PSoC, USB, 存储器，时钟，图像传感器等产品，旨在为全球消费类电子和通讯产品等提供品质优良的芯片和解决方案。目前，塞普锐思公司在可编程SoC，USB（有线和无线），存储器，通讯时钟等产品方面处于行业领先地位。
基于业务的飞速增长和更好的服务于亚太客户，塞普锐思公司正在扩大在中国的研发和服务团队。公司位于张江集电港，包括集成电路设计，方案中心，市场和销售，Fab等。
公司有良好的企业文化，非常注重员工的个人发展，能够提供完善的培训体系，并有出国培训机会。
塞普锐思公司已于纽约股票交易所上市，代号"CY"。
请登录公司网站了解更多信息:http://www.cypress.com
Cypress Semiconductor Co., Ltd delivers high-performance, mixed-signal, programmable solutions that provides customers with rapid time-to-market and exceptional system value. Cypress offerings include the flagship PSoC programmable system-on-chip families and derivatives such as PowerPSoC® solutions for high-voltage and LED lighting applications, CapSense® touch sensing and TrueTouchTM solutions for touchscreens. Cypress is the world leader in USB controllers, including the high-performance West Bridge® solution that enhances connectivity and performance in multimedia handsets. Cypress is also a leader in high-performance memories and programmable timing devices. Cypress serves numerous markets including consumer, mobile handsets, computation, data communications, automotive, industrial.
Based on the rapid business growth and in order to provide better services for its Asian customers, Cypress is now expanding the sales/marketing and research/development teams in China. Cypress China currently consists of IC design, Applications, Sales and marketing, Manufacturing, TE/PE and Finance departments and is located at ZhangJiang Riverfront Harbor.
Cypress has an educational and US-based company culture, employee training plans and salary benefit systems.
Cypress employs nearly 4,000 people worldwide with headquarters located in Silicon Valley. Its shares are listed on the NYSE (CY).
More information about Cypress is available at http://www.cypress.com