北京招聘

Responsibility:

We are currently looking for Senior Design Verification Engineers who will be responsible for all aspects of verification on next generation integrated processors (CPU + GPU + Multi Media) chipset, including developing testbenches, modeling, assertions/checkers/monitors, test plan & test development, regressions, and infrastructure development. Responsibility includes participating in the pre-silicon blocks, chip, multi-chip and system level verification strategy:

- Verification of SoC level design using random methodologies - Test Planning, Implementation and Execution.

- Develop System Verilog (OVM) random sequences and methods.

- Maintain and Interface with existing random generators, models and APIs

- Integration of random modules to various testbenches.

- Executing verification through directed and random tests for its functionality and interface protocols and tracking bug reports. Creation of the needed test libraries, test API, simulation models. Debugging regression failures and identify the cause.

- Strong documentation and communication skills.

- Ability to work well in a dynamic, fast-paced, pressure filled, across multiple sites North America and Asia

- Flexible in terms of responsibilities and hours.

Requirement:

- 3+ years experience in complex ASIC/SOC Design Verification, direct experience in SOC or Processor (GPU or CPU) or Industry bus standard (PCI-e, MC, HT) or multimedia/video is preferred.

- Good knowledge of SystemVerilog and OVM is a big plus.

- Good knowledge of Verilog/C/C++/System C/SystemVerilog.

- 2+ years experience in Verification.

- Verification insights into random techniques.

- Verification of large scale ASICs.

- Working knowledge of x86 assembly programming is an asset.

- Experience in power verification is an asset.

- Verification of Virtualization Components is an asset.

- Strong C and C++ software development and scripting languages (Perl, C Shell, Makefile, ...) experience.

- Strong background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA).

Design Engineer

Responsibility:
· Participate in SOC IC project logic design
· Working with architect to define chip level specification, including clock and power targets, IP selection, floorplan review etc.
· Develop RTL code for chip level in Verilog HDL and make sure functional correct and reusable for different configuration.
· Synthesis and deliver netlist that meeting timing, area and power requirement. Help PD on the floorplanning and close timing.
· Work very closely with physical design engineers to help on floorplan, timing closure, power design validation and etc.
· Bring-up ASIC. Guide hardware team to solve design problem in application. Help to short Time-To-Market.



Requirement:
· MS degree of EE.
· Communicate effectively within a global business environment (must be proficient in both spoken and written English)
· Experience in logic design, synthesis, static timing analysis.
· Experience with ASIC EDA tools used in synthesis, simulation, static timing analysis, and formal verification
· Familiar with unix/linux and scripts (tcl, perl etc.)
· Excellent technical troubleshooting and demonstrated problem solving skills
· Possesses specialized knowledge of Computer architecture and computer arithmetic (a plus)
· Possesses specialized knowledge of Computer graphic knowledge (a plus)

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