北京招聘

Job Title: Senior Design Engineer

Department: Central Engineering-Digital

Location: Beijing/ Nanjing

Qualification:

MS/Ph.D. in Electrical Engineering

Proficient in digital design – RTL, Verilog, verification, synthesis, formal, timing closure, ECO

Description:

Senior design engineer responsible for the design, verification and evaluation of digital circuits in high-speed data communication ICs. Responsibilities include: specification, design RTL coding, verification, synthesis, timing closure, chip integration, test pattern development and post silicon debugging. Knowledge of Ethernet physical layer PCIE, SerDes is a plus.

We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you. Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.

Website: **********************