世界知名德资公司征MEMS验证verification leader
上海任仕达人才服务有限公司
- 公司规模：150-500人
- 公司性质：外资(欧美)
- 公司行业：专业服务(咨询、人力资源、财会)
职位信息
- 发布日期：2013-05-14
- 工作地点：上海
- 招聘人数：若干
- 工作经验：五年以上
- 学历要求：本科
- 语言要求：英语精通
- 职位类别：IC验证工程师
职位描述
Title: Verification engineering leader
Responsibilities
Roles and Responsibilities
? Verification of digital and mixed-signal circuits (module-level and chip-level)
? Definition of verification plans and verification environments for mixed-signal sensor systems
? Tracking and management of verification progress and coverage
? Close cooperation and interaction with international teams
Qualification Requirement
? (e.g. Education, Working Experience, Knowledge, Skills, Language, Competence, etc)
? Bachelor or master degree in (Micro-)Electronics, Communications, Computer Engineering or equivalent, 3+ years
? Experience of large scale IP/SoC verification, or experience in development of automated test-bench
? Hands-on experience of C/C++ programming language is preferred
? Self motivated, excellent communication skills and a real team player
? English written and verbal
? Understand of / experience with at least one of following domains:
? Make-file/Perl/Python scripting
? SystemVerilog or SystemC or Specman-e verification language, experience in UVM is preferred
? VerilogAMS, Cadence AMSD, Mixed-signal simulation
Responsibilities
Roles and Responsibilities
? Verification of digital and mixed-signal circuits (module-level and chip-level)
? Definition of verification plans and verification environments for mixed-signal sensor systems
? Tracking and management of verification progress and coverage
? Close cooperation and interaction with international teams
Qualification Requirement
? (e.g. Education, Working Experience, Knowledge, Skills, Language, Competence, etc)
? Bachelor or master degree in (Micro-)Electronics, Communications, Computer Engineering or equivalent, 3+ years
? Experience of large scale IP/SoC verification, or experience in development of automated test-bench
? Hands-on experience of C/C++ programming language is preferred
? Self motivated, excellent communication skills and a real team player
? English written and verbal
? Understand of / experience with at least one of following domains:
? Make-file/Perl/Python scripting
? SystemVerilog or SystemC or Specman-e verification language, experience in UVM is preferred
? VerilogAMS, Cadence AMSD, Mixed-signal simulation
公司介绍
www.randstad.cn
联系方式
- 公司地址：梅园路77号
- 邮政编码：200070