北京招聘

Position description:

Run simulation for module and chip level (mainly in SerDes IP/Chip), work closely with designer;

Develop and execute verification plan;

Define, implement and analysis functional/code coverage;

Develop/maintain/enhance environment (TB/tools/scripts/flow).

Requirement:

Proficient and experienced in one of the high level verification methodology (VMM, UVM);

Experienced with hardware verification language (Vera, SystemC, SystemVerilog)

Proficient with Verilog HDL;

Proficient with at least one scripting languages, e.g. Csh, Bash, Perl, Tcl

Familiar with ASIC design flow

Master degree in EE

Experienced in SerDes PHY(USB3, SATA, SAS, PCIE etc) is a plus.

We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you. Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.

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