北京招聘

Job Title:(Senior) Design Engineer
Department:SOC Platform
Location:Shanghai and Chengdu

1. Experienced with IP design, verification and SoC integration.
2. Hands-on experience with standard design flow and tools on various design phases, including documentation, coding, lint, version control and RTL/gate simulation.
3. Experience with SystemVerilog and UVM is a plus.
4. Experience with FPGA prototyping is a plus.
5. Must be able to communicate in both written and spoken English.
6. Good team work spirit and problem solving skills

Description:

This position is in a leading edge fast growing US semiconductor company. As a senior design engineer, the individual will have the opportunity to work closely with USteam on exciting IPs on latest and greatest design methodology and flow.

Responsibility includes:
1. Participating architect, micro-architect, and execution of the projects.
2. RTL coding, Verification, Logic simulations, synthesis, timing, silicon bring-up, etc
3. Documentation
4. Work closely with FPGA team for pre-silicon prototyping.
5. Work closely with software team for driver developments
6. Traveling to US is not mandatory, but sometimes required

We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you. Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.

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