Physical Design Power Optimization Engineer
超威半导体(中国)有限公司
- 公司规模:1000-5000人
- 公司性质:外资(欧美)
- 公司行业:电子技术/半导体/集成电路
职位信息
- 发布日期:2021-06-04
- 工作地点:北京
- 招聘人数:若干人
- 工作经验:5-7年经验
- 学历要求:本科
- 职位类别:数字后端工程师
职位描述
THE ROLE:
Power is a more and more hot topic in IC design. We are a power/performance/area optimization methodology team. In this position, you will work with global team especially physical design team for GPU chips physical design power optimization/reduction. Focus on physical design methodology optimization/update to improve chip Power and Performance/Area (PPA), including RTL -> Syn>place&route iteration/optimizing.
The individual is expected to be an expert in physical design areas, it is a plus to have strong ability in multiple aspects in FrontEnd or RTL coding experience or Synthesis. The individual is expected know backend power optimization very well, be very familiar with physical design power reduction methodology, not limited to PD but also can be Frond-end power reduction method.
THE PERSON:
Strong selfmotivation for technical topics, quick and deep learner, strong communication skill within global engineering team, strong team spirit help and support team members.
KEY RESPONSIBILITIES:
? Develop state of art physical design power optimization methodology
? Verify and test the power optimization methodology in physical design flow.
? Closely cowork with GPU chip project design team, help/support/drive them adopt the power optimization methodology
PREFERRED EXPERIENCE:
? Preferred 8+ years or more years of experience in physical design in digital ASIC chips
? Be very familiar with physical design power optimization methodology, (eg. Clock-gating, power-gating, activity aware PnR, power friendly floorplan, DVFS, multibit re-banking de-bandking, scan path power …)
? Expert in BackEnd (physical design) EDA tools, especially the power calculation/optimization tools,
? strong flow develop and custom script develop ability
? Knowledgeable in all aspects of deep submicron ASIC design flow
? Successfully gone through several complete product development cycles
? work well with crossfunctional teams
? Good listening, writing and speaking English
? Good communication skills, strong interpersonal skills and the flexibility
ACADEMIC CREDENTIALS:
? preferred MSEE with 8+ years or Bachelor with 10+ years of industrial experience in ASIC design
LOCATION:
? Beijing
职能类别:数字后端工程师
公司介绍
联系方式
- Email:bella.yu@amd.com
- 公司地址:上海-浦东新区 张江 环科路669号凯瑞大厦