Senior IC Design Backend Engineer
飞思卡尔半导体(中国)有限公司上海分公司
- 公司性质：外资(欧美)
- 公司行业：电子技术/半导体/集成电路
职位信息
- 发布日期：2013-03-26
- 工作地点：上海-浦东新区
- 招聘人数：1
- 工作经验：五年以上
- 学历要求：本科
- 职位类别：集成电路IC设计/应用工程师
职位描述
Senior IC Design Backend Engineer
Freescale Semiconductor is a global leader in the design and manufacture of embedded semiconductors for the automotive, consumer, industrial and networking markets. Our products are all around us, you touch them every day.
The most versatile platform for multimedia and display applications, Freescale ARM?-based i.MX processors deliver an optimal balance of power, performance and integration to enable next-generation smart devices.
The i.MX 6 Series unleashes a scalable multicore platform that includes single-, dual- and quadcore families based on the ARM? Cortex?-A9 architecture for next-generation consumer, industrial and automotive applications. By combining the power-efficient processing capabilities of the ARM Cortex-A9 architecture with bleeding edge 3D and 2D graphics, as well as high-definition video, the i.MX 6 Series provides a new level of multimedia performance to enable an unbounded next generation user experience.
The success of our engineers is driven by their passion about technology, innovation and ambition in growing their soc design expertise; this is our contribution to Freescale adventure to make the world a smarter place.
Would you like to design world class multimedia chips produced by advanced process like 28nm? Are you already working with advanced digital circuits implementation tools and you would like new features and improvements?
Join us! We are making here the next generation ARM Cortex-A15 based multicore platform i.MX7 Series multimedia processors.
To ensure your successful performance in this role, the following working experience is required: floor-planning, power planning, place and route, STA, IR drop and signal integrity, DRC/LVS. You should have good understanding on soc backend flow and process, special for partition flow.
It will bring you an advantage if you have experience with synthesis.
Joining Freescale will assure you a rewarding performance and the opportunity to be part of the most innovative soc team in Freescale Semiconductor Inc. Beside an attractive salary package, you will have the challenge to patent best ideas in the soc domain, in a secure, pleasant and dynamic work environment.
You can be part of the soc backend team, to design very complex world class multimedia chips. You will work with very experienced engineers, complete challenging tape out, covering all aspects of soc backend design, from the RTL to GDS flow.
Responsibility:
1. Work with the global design team to do complex SOC physical implementation for deep submicron design.
2. Participates in chip level and block level backend design for complex SOC designs.
3. Responsible for RTL to GDS flow including CPF definition, logic/physical synthesis, die size estimation, floor-planning, power planning, CTS, place and route, STA, signal integrity, timing closure, formal verification, DFM, DRC/LVS etc.
4. Play a critical role in high performance design timing closure.
Qualifications:
1. University degree in microelectronics engineering or equivalent, master degree or above is preferred;
2. 5+ years industry experience, at least 3 years in physical design role in submicron projects;
3. Good understanding on backend flow and process, special for partition flow is must;
4. Successful completion of 5+ physical design projects (at least one at 65nm or below);
5. Experience on Cadence, Synopsys, Magma, Mentor tools;
6. Hands on experience on floorplan, place and route, STA, IR drop and signal integrity, DRC/LVS is must;
7. Hands on experience on synthesis is preferred;
8. Good communication skills, English language proficiency.
Freescale Semiconductor is a global leader in the design and manufacture of embedded semiconductors for the automotive, consumer, industrial and networking markets. Our products are all around us, you touch them every day.
The most versatile platform for multimedia and display applications, Freescale ARM?-based i.MX processors deliver an optimal balance of power, performance and integration to enable next-generation smart devices.
The i.MX 6 Series unleashes a scalable multicore platform that includes single-, dual- and quadcore families based on the ARM? Cortex?-A9 architecture for next-generation consumer, industrial and automotive applications. By combining the power-efficient processing capabilities of the ARM Cortex-A9 architecture with bleeding edge 3D and 2D graphics, as well as high-definition video, the i.MX 6 Series provides a new level of multimedia performance to enable an unbounded next generation user experience.
The success of our engineers is driven by their passion about technology, innovation and ambition in growing their soc design expertise; this is our contribution to Freescale adventure to make the world a smarter place.
Would you like to design world class multimedia chips produced by advanced process like 28nm? Are you already working with advanced digital circuits implementation tools and you would like new features and improvements?
Join us! We are making here the next generation ARM Cortex-A15 based multicore platform i.MX7 Series multimedia processors.
To ensure your successful performance in this role, the following working experience is required: floor-planning, power planning, place and route, STA, IR drop and signal integrity, DRC/LVS. You should have good understanding on soc backend flow and process, special for partition flow.
It will bring you an advantage if you have experience with synthesis.
Joining Freescale will assure you a rewarding performance and the opportunity to be part of the most innovative soc team in Freescale Semiconductor Inc. Beside an attractive salary package, you will have the challenge to patent best ideas in the soc domain, in a secure, pleasant and dynamic work environment.
You can be part of the soc backend team, to design very complex world class multimedia chips. You will work with very experienced engineers, complete challenging tape out, covering all aspects of soc backend design, from the RTL to GDS flow.
Responsibility:
1. Work with the global design team to do complex SOC physical implementation for deep submicron design.
2. Participates in chip level and block level backend design for complex SOC designs.
3. Responsible for RTL to GDS flow including CPF definition, logic/physical synthesis, die size estimation, floor-planning, power planning, CTS, place and route, STA, signal integrity, timing closure, formal verification, DFM, DRC/LVS etc.
4. Play a critical role in high performance design timing closure.
Qualifications:
1. University degree in microelectronics engineering or equivalent, master degree or above is preferred;
2. 5+ years industry experience, at least 3 years in physical design role in submicron projects;
3. Good understanding on backend flow and process, special for partition flow is must;
4. Successful completion of 5+ physical design projects (at least one at 65nm or below);
5. Experience on Cadence, Synopsys, Magma, Mentor tools;
6. Hands on experience on floorplan, place and route, STA, IR drop and signal integrity, DRC/LVS is must;
7. Hands on experience on synthesis is preferred;
8. Good communication skills, English language proficiency.
公司介绍
恩智浦半导体（纳斯达克代码：NXPI）致力于通过先进的安全连结及基础设施解决方案为人们更智慧安全、轻松便捷的生活保驾护航。作为全球领先的嵌入式应用安全连接解决方案领导者，恩智浦不断推动着互联汽车、端对端安全及隐私、智能互联解决方案市场的创新。恩智浦拥有超过60年的专业技术及经验，拥有29,000名员工，业务遍及30多个国家，2019年的营业额达88.8亿美元。