Design Verification Engineer
超威半导体(中国)有限公司
- 公司规模:1000-5000人
- 公司性质:外资(欧美)
- 公司行业:电子技术/半导体/集成电路
职位信息
- 发布日期:2021-01-10
- 工作地点:北京
- 招聘人数:若干人
- 工作经验:5-7年经验
- 学历要求:本科
- 职位类别:IC验证工程师 数字前端工程师
职位描述
Beijing GPU SOC team is looking for DV engineer that will work on design verification of cutting edge 3D GPU projects, to cover PCIe/HSIO controller integration and SOC level feature verification including data-path and interrupt, power management, etc.
RESPONSIBILITIES:
Interface with global architecture and design teams, understand graphics SoC design and feature set
SoC testbench and infrastructure development and maintenance for integrated IP DV components
PCIe/HSIO controller IP RTL integration to SOC, including connectivity/design partition/sanity test bring up
Implement directed and random test cases and TB in C++/UVM, as well as checkers and assertions
Support PCIe/HSIO controller debugging at SoC level for other DV domains
Help to improve DV environment building flow
REQUIREMENTS:
Rich experience of complex ASIC DV flow from plan to coverage, tech lead experience is desired
knowledgeable in C++ & SV, familiar with script languages like Ruby/Perl/Makefile
Strong problem solving, communication and analytical thinking skills
Knowledge on computer architecture and PCIe devices is highly preferred
Good knowledge on verification methodologies like UVM is a big plus
Experience in power-aware verification is an asset
Be able to provide Technical mentoring and guidance to junior engineers
EDUCATION:
Master with at least 6 years or Bachelor with at least 8 years working experience in ASIC area
公司介绍
联系方式
- Email:bella.yu@amd.com
- 公司地址:上海-浦东新区 张江 环科路669号凯瑞大厦