北京招聘

RESPONSIBILITIES

    

• Develop verification test bench components for chip/module level using System Verilog
• Use high level language concepts (Object oriented, UVM/OVM etc) to develop extendable environment.
• Define and execute detailed verification plan from spec working with architects, designers, system engineers.
• Incorporate code-coverage, functional coverage, assertions, cover-groups etc to achieve 100% verification completeness prior to tape-out.
• Debug tests, run gate level simulations

    

QUALIFICATIONS

    

• Organized and creative thinker, motivated, and independent learner who can multitask in a dynamic environment, able to create and implement new solutions where required
• good at building verification environments preferably using the verification subset of high level languages like System Verilog (UVM) is a plus
• familiar with System Verilog
• Experience with simulators like ncVerilog (Incisive), VCS simvision, IMC,modelsim etc
• Good written and oral communication skills. Ability to clearly document plans.
• Ability to interface with different teams and prioritize work based on project needs.

    

EDUCATION

    

MS with 1+ years’ experience in Electrical Engineering or Micro Electronic

欢迎2021应届生或有1~2年工作经历同学投递简历~

TI China
TI China began operations in 1986 in Beijing. Today, we employ more than 2200 employees in our 17 sales & applications offices, three research & development centers, one integrated manufacturing center with wafer fab, assembling & testing and bumping facilities, as well as one product distribution center. Our unparalleled resources deployed in China enable us to provide strong support in every step from design and manufacturing to sales and product distribution to over 17000 customers in China across industrial, automotive, communications, personal electronics and enterprise market. Our engineers and professionals are committed to shaping the future of electronics through semiconductors and helping our customers succeed in China and around the world.