北京招聘

Responsibility:

• Work with the global design team to do complex SOC physical implementation for deep submicron design.
• Participates in block level backend design for complex SOC designs.
• Responsible for RTL to GDS flow including CPF definition, logic/physical synthesis, die size estimation, floor-planning, power planning, CTS, place and route, STA, signal integrity, timing closure, formal verification, DRC/LVS/DFM physical verification etc.
• Play a critical role in high performance design timing closure.

Qualifications:

• University degree in microelectronics engineering or equivalent, master degree or above is preferred;
• Prefer to have basic experience in IC physical implementation.
• Experience using backend EDA tools; i.e. Cadence Genus/Innovus/Tempus, Synopsys DC/ICC2, Mentor Graphics Calibre etc is a plus.
• Relevant experience in the area of digital circuit design is a plus.
• Good knowledge of C/C++, Perl/TCL. Script in Linux/Unix environment is a plus.
• Good language skill in English. Passed CET- 6.

NXP Semiconductors N.V. (NASDAQ: NXPI) enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better, and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the automotive, industrial & IoT, mobile, and communication infrastructure markets. Built on more than 60 years of combined experience and expertise, the company has over 29,000 employees in more than 30 countries and posted revenue of $8.88 billion in 2019.