北京招聘

We have multiple directions for ASIC Engineer development, including IP design/verification, SOC design/verification, ASIC Physical Design, DFT Design, FPGA/Emu, etc.  We share them in a single JD

What you’ll be doing:

1. Micro architecture design.

2. RTL (Verilog) coding.

3. Design implementation using Synopsys/Cadence tools.

4. Simulate, debug and write tests to verify design functionality and performance. (IP/SOC/FPGA/EMU design/verification direction)

5. Synthesis/Netlist quality check/Formal verification, Chip partitioning, Timing constraints development for various function/dft modes, Co-work with PR on floorplan and achieve timing closure, Timing sign off.  (PD Direction)

6. Responsible for DFT verification environment setup, own DFT verification and bringup tasks for Clocks, Boundary Scan, Analog and MBIST, Scan, etc. (DFT Direction)

7. FPGA/EMU synthesis, partitioning and emulating using Synopsys/Cadence etc. Tools and FPGA/EMU ‘s infrastructure flow implementation (FPGA/ EMU direction)

8. Methodology in any of above areas.

What we need to see:

1. MS degree from EE/CS or related majors from a prestigious university.

2. Good knowledge in digital circuit design.

3. Experience in using Verilog HDL.

4. Experience in various of ASIC EDA tools.

5. Fluent in English reading and writing.

6. Self-motivated, good team player.

Ways to stand out from the crowd:

1. Proven ability to work independently as well as in a multi-disciplinary group environment

2. Good command of C/C++ programming language.

3. Mastery in one of the below areas

 1) Video codec.

 2) Encryption/Decryption.

 3) Processor architecture.

 4) Signal/image processing.

 5) Pattern recognition/machine learning.

 6) Data science.

 7) System on Chip.

 8) Memory interface.

4. Understand ASIC design flow, hands-on experience in using industrial standard EDA tools is a plus.

5. Basic DFT knowledge including Boundary Scan, 1500, MBIST, Scan, ATPG is a plus

6. Hand-on experience in EDA software from Synopsys (DC/PT/Formality), Cadence (RC compiler/LEC) is a plus

7. Proficient user of script language like Perl, Python or TCL is plus

8. Experienced in FPGA/EMU related implementation is a plus

9. Experienced in Linux PCIE driver or other SW works is a plus

10. Experienced in SystemC or UVM or SV or SCE-MI or other standards is a plus

We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.

NVIDIA—AI计算公司中的领导者
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