(Senior) Physical Design Engineer
美满电子科技(Marvell)
- 公司规模:500-1000人
- 公司性质:外资(欧美)
- 公司行业:电子技术/半导体/集成电路
职位信息
- 发布日期:2014-08-19
- 工作地点:成都
- 招聘人数:若干
- 学历要求:本科
- 语言要求:英语熟练
- 职位类别:硬件工程师
职位描述
Job Title: (Senior) Physical Design Engineer
Department: COT-PD
Location: Chengdu
Qualifications:
BS/MS in EE/CS required.
Three or more years of hands-on experience on IC physical design, verification and tapeouts.
Proven track records of working independently on place-and-route project running and DRC/LVS debugging skills
Experience with Synopsys or Cadence place-and-route tools on physcial implementation..
Knowledge of Calibre or Hercules runsets.
Good programming skill. Capable of writing TCL or Perl.
Familiar with synthesis, static timing analysis.
In-depth understanding of fabrication processing steps used in major fabrication industries.
Self-motivated team worker, good verbal and written communication skills in English.
Experience with DFT and verification is preferred.
Responsibilities:
IC implementation from gate level netlist to GDS, including floorplanning, place and route, cts, timing closure, and physical verification.
Crosstalk analysis, power analysis, and static timing analysis.
Write scripts in TCL or Perl to improve productivity.
As a key member of central physical design team, your will play am important role in assisting multiple Marvell design groups in physical design, verification (DRC/LVS/ERC/Antenna) and tapeout.
You will have the opportunity to help develop next generation physical implementation flow for cutting-edge technology.
Future development in synthesis, DFT, and verification is possible.
Department: COT-PD
Location: Chengdu
Qualifications:
BS/MS in EE/CS required.
Three or more years of hands-on experience on IC physical design, verification and tapeouts.
Proven track records of working independently on place-and-route project running and DRC/LVS debugging skills
Experience with Synopsys or Cadence place-and-route tools on physcial implementation..
Knowledge of Calibre or Hercules runsets.
Good programming skill. Capable of writing TCL or Perl.
Familiar with synthesis, static timing analysis.
In-depth understanding of fabrication processing steps used in major fabrication industries.
Self-motivated team worker, good verbal and written communication skills in English.
Experience with DFT and verification is preferred.
Responsibilities:
IC implementation from gate level netlist to GDS, including floorplanning, place and route, cts, timing closure, and physical verification.
Crosstalk analysis, power analysis, and static timing analysis.
Write scripts in TCL or Perl to improve productivity.
As a key member of central physical design team, your will play am important role in assisting multiple Marvell design groups in physical design, verification (DRC/LVS/ERC/Antenna) and tapeout.
You will have the opportunity to help develop next generation physical implementation flow for cutting-edge technology.
Future development in synthesis, DFT, and verification is possible.
公司介绍
We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you. Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.
Website: **********************
Website: **********************
联系方式
- Email:jiangrr@marvell.com
- 公司地址:地址:span安德门大街57号(楚翘城)7幢3层