北京招聘

Responsibilities:

- Create the RTL architecture for the algorithm.

- RTL coding, new logic design, simulation, synthesis. 

- Work closely with algorithm engineer to develop/debug new IP. 

Requirements:

- Bachelor degree or above, major in Electronic Engineering/Computer Science or other related discipline.

- Minimum 3 years’ relevant working experience on IP simulation and debug process using VCS and Verdi.

- Very familiar with the Verilog HDL language, know VHDL is a plus.

- Design and test experience on MCU controller design is a plus.

- Very familiar with digital design EDA tools such as DC,PT,Formality. 

- Familiar with the flow of the IC design. 

- Strong communication skills.

NXP Semiconductors N.V. (NASDAQ: NXPI) enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better, and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the automotive, industrial & IoT, mobile, and communication infrastructure markets. Built on more than 60 years of combined experience and expertise, the company has over 29,000 employees in more than 30 countries and posted revenue of $8.88 billion in 2019.