IP Design Engineer
超威半导体(中国)有限公司
- 公司规模:1000-5000人
- 公司性质:外资(欧美)
- 公司行业:电子技术/半导体/集成电路
职位信息
- 发布日期:2020-03-18
- 工作地点:北京
- 工作经验:招若干人
- 学历要求:03-17发布
- 语言要求:不限
- 职位月薪:40-60万/年
- 职位类别:高级硬件工程师 硬件工程师
职位描述
IP Designer
THE ROLE:
It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
THE PERSON:
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, driving execution of quality and timely result, capability to solve complex, novel and no-recurring problems and decision-making on critical technical areas
KEY RESPONSIBILITIES:
- Work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC projec
- technical leading on the following tasks from time to time: specification, top level SOC design tasks, HDL coding, etc
PREFERRED EXPERIENCE:
- Master in Electrical Engineering, Computer Science or related
- Deep understanding on ASIC design verification flow
- RTL coding with Verilog/System Verilog
ACADEMIC CREDENTIALS:
MSEE with minimum of 6 years, or BSEE with minimum of 8 years experiences in digital ASIC/SOC design verification
LOCATION:
Shanghai/BeiJing
公司介绍
联系方式
- Email:bella.yu@amd.com
- 公司地址:上海-浦东新区 张江 环科路669号凯瑞大厦