IP Design Verification Manager
超威半导体(中国)有限公司
- 公司规模:1000-5000人
- 公司性质:外资(欧美)
- 公司行业:电子技术/半导体/集成电路
职位信息
- 发布日期:2019-11-04
- 工作地点:上海-浦东新区
- 招聘人数:若干人
- 工作经验:无工作经验
- 学历要求:本科
- 职位月薪:3-4万/月
- 职位类别:IC验证工程师
职位描述
What you do at AMD changes everything
At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, Immersive platforms, and the data center.
Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
Job Summary:
NBIO subsystem DV Manager, responsible for managing NBIO subsystem DV team with more than 10 engineers in Shanghai, co-work with global NBIO DV team, develop and verify NBIO subsystem.
Job Responsibilities:
AMD NBIO (North Bridge IO) team delivers industry leading high performance interconnects IP subsystem for all AMD products including dGPU, APU, Server and Game consoles. You'll be working with the global team on NBIO container development and verification.
Responsibility:
* Manage team daily execution.
* Lead team to complete develop NBIO subsystem drop and verify NBIO container.
* Global communication and alignment.
Job Requirements:
Education& Qualifications
Candidate is preferred to be MSEE with minimum of 8 years, or BSEE with minimum of 10-year experience in digital ASIC/SOC design verification, more than 2 years’ management experience.
Experience
1. Good people manager skills
2. Good communication skills in both Chinese and English
3. Complex IP/ASIC/SOC design verification background, direct experience in IP/SOC or Processor (CPU or GPU) or Industry bus standard (PCI-e, HT, USB, DDR, DisplayPort)
4. Solid background with ASIC design verification flow and multiple ASIC tape out experience
5. Solid knowledge on SystemVerilog, C/C++, Verilog
6. Solid knowledge on scripting language like perl, python, ruby
7. Solid knowledge on UVM/OVM
8. Solid background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA)
9. Knowledge on High speed IO/PCIE is a big plus
10. Experience in project management is a big plus
职能类别:IC验证工程师
公司介绍
联系方式
- Email:bella.yu@amd.com
- 公司地址:上海-浦东新区 张江 环科路669号凯瑞大厦