北京招聘

Responsibility:   

Work together with algorithm team and design team to develop testplan and testcases for various blocks in our Read Channel products.   

Maintain and help improve UVM based verification environment.      

Develop checker/driver and test cases to verify read channel designs.  

Research on some advanced verification technology such as assertion based formal verification.  

  

Requirement:

Major in EE, CS or related.

Familiar with Verilog and RTL design

Familiar with System-Verilog and UVM verification methodology

Familiar with script languages(perl,tcl,sh etc.) is a plus

Familiar with digital signal processing knowledge is a plus

Good problem solving and communication skills

Good written and spoken English. Be able to work together with global team.

  

    

We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you. Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.

Website: **********************