北京招聘

RESPONSIBILITIES:

• IP/Chip level verification:
• Develop Test Plan and new test cases;
• Develop function coverage points;
• Maintain regression；
• Global team co-work;

REQUIREMENTS:
? 3years’ + for Master or 5 years’ + for Bachelor work experience
? Design Verification experience in C++/UVM for IP or SoC chip level
? ASIC Verification with knowledge of System Verilog , Verilog, script language, like: perl, shell
? Have Ethernet/AXI bus experience is better
? Knowledge of Unix and Linux is highly desired
? Strong verbal and written communication skills in English
? Strong teamwork skills with good human relationship

We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you. Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.

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