北京招聘

Responsibilities:

? Responsible for DFT architecture definition and DFT planning for complex SoC design. 

? Perform design implementation and verification on test related modules, scan chain and test compression insertion, memory build in self test, logic build in self test, JTAG/Boundary scan, etc. 

? Support design team to improve the testability of IP and chip to meet test coverage requirement. 

? Responsible for scan, BIST and boundary scan pattern generation and verification.

? Work with test engineer and product engineer to define the DFT requirement, deliver test patterns and provide support on silicon test debug.

Requirements:

? Bachelor or master degree in Electronics, Communications, Microelectronics Engineering, Computer Science or relevant disciplines.

? Strong logic design and verification background with good debugging capability, experience in digital design with good knowledge of SoC design flow, including RTL coding, simulation, synthesis, DFT and silicon test. 

? Familiar with industrial standard DFT methodology and tools, experience in scan, ATPG, memory BIST, LBIST, Boundary scan, etc.

? Knowledge in ATE  and experience in silicon validation on tester is plus. 

? Analog/flash design knowledge/background is strong plus.

? Nice to have skills: script language like perl, tcl.

NXP Semiconductors N.V. (NASDAQ: NXPI) enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better, and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the automotive, industrial & IoT, mobile, and communication infrastructure markets. Built on more than 60 years of combined experience and expertise, the company has over 29,000 employees in more than 30 countries and posted revenue of $8.88 billion in 2019.