Feint Engineer前端综合工程师
超威半导体(中国)有限公司
- 公司规模:1000-5000人
- 公司性质:外资(欧美)
- 公司行业:电子技术/半导体/集成电路
职位信息
- 发布日期:2019-11-28
- 工作地点:上海-浦东新区
- 招聘人数:若干人
- 工作经验:5-7年经验
- 学历要求:本科
- 职位类别:集成电路IC设计/应用工程师
职位描述
Job Responsibilities:
- Responsible for Front-End chip implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design.
- Responsible for ASIC design methodology and flow development, interfacing with EDA vendors on technology.
Skills & Experience
- More than 6 years of relevant experience
- Familiar with Verilog RTL design and has experience of large digital ASIC project.
- Familiar with front-end EDA tools and flows (Design compiler, PrimeTime, Conformal,Verde)
- Familiar with unix/linux and scripts (tcl, perl etc.)
- Fluent English on talking, presentation and writing documents.
- Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager.
职能类别:集成电路IC设计/应用工程师
公司介绍
联系方式
- Email:bella.yu@amd.com
- 公司地址:上海-浦东新区 张江 环科路669号凯瑞大厦