Senior RFIC Layout Engineer
翱捷科技(上海)有限公司
- 公司规模:500-1000人
- 公司性质:合资
- 公司行业:电子技术/半导体/集成电路
职位信息
- 发布日期:2020-12-30
- 工作地点:上海-浦东新区
- 工作经验:招若干人
- 学历要求:12-30发布
- 语言要求:不限
- 职位类别:版图设计工程师
职位描述
Key Qualifications:
1. Chip top and block-level floorplanning in high frequency and high switching-noise environments.
2. Drawing complex layouts of CMOS RF and Analog Mixed-Signal cells and blocks
3. Solid understanding of physical, electrical, and DFM rules for deep-submicron CMOS processes
4. Experience in custom RF/analog layout with extensive knowledge of deep sub-micron CMOS (40nm, 28nm, FinFET, etc.)
5. Knowledgable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing
6. Solid understanding of RC delay, electromigration, and coupling
7. Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD, WPE, etc.
8. High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc.
9. Knowledge of CADENCE layout tools
10. Excellent communication skills and able to work with cross-functional teams
11. Capability to lead other layout engineers for top-level integration
12. Ability to recognize failure prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems
13. Scripting skills in PERL or SKILL are a plus, but not required
Requirements: 5+ years industry experience in RF and analog mixed-signal layout design of deep submicron CMOS circuits, including LNA, PA, mixer, bandgap references, filters and PLLs. Extensive experience in silicon tape-out.
Education: BSEE and above
职能类别:版图设计工程师
公司介绍
ASR作为一家高科技公司,经过连续几年的产品研发,以及对Marvell移动芯片部门的收购和技术整合,ASR已具备完整、强大的移动智能终端芯片和物联网芯片的研发和产业化能力。随着市场的成熟,公司将持续加大物联网和5G领域的投资,为移动通讯、物联网和智能终端市场提供更优秀的产品方案和高效的技术支持,力争成为业界一流水平的国产芯片提供商。
联系方式
- 公司地址:地址:span高新区天府四街199号长虹科技大厦A座25楼