北京招聘

资深数字后端设计

地点：上海/北京

Description:

- Perform physical design implementation, including floorplan, power grid design, P&R, CTS, timing closure, power/signal integrity signoff, DRC/LVS/Antenna, EM/IR signoff, DFM Closure.

- Participate in or lead next generation PHY IP or SOC physical design, methodology and flow development.

Requirements:

- BS degree with 6+ years of experience, MS degree with 3+ years of experience in electrical engineering, microelectronics.

- Experienced with ASIC design flow, hierarchical physical design strategies, and methodologies and understand deep sub-micron technology issues.

- Solid knowledge on low power design, static timing analysis, EM/IR-Drop/crosstalk analysis, physical verification, DFM. Successful track records of taping out complex, 16nm/10nm/7nm chips.

- Automation and programming-minded, solid coding experience in Makefile/Tcl/Tk/Perl.

- Self-motivated, able to work independently or as a team player, excellent verbal and written communication skills in English.

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