北京招聘

Responsibilities：

?       Establishes and maintains standardization DFT methods and flow for SoC projects

?       Responsible for the design, validation, and implementation of all chip DFT test scenarios (including scan/MBIST/boundary scan/IP test, etc.)

?       Responsible for the whole chip DFT test plan, test structure definition, write test document

?       Complete the DFT logic design and implementation of chip by advanced DFT EDA tools

?       Support logic and physical design teams to complete DFT-related power, timing signoff

Generates, simulates, debugs test vectors, help testing vendor to develop, debug and optimize the test program for chip mass production.

Qualifications:

?       5+ years’ experience in DFT design projects, bachelor degree or above, master degree preferred;

?       Familiar with mainstream DFT design EDA tools and implementation principles as well as basic implementation methods;

?       3+ experience in the process project of DFT design starting from the net table;？

?       Can use simulation tools to test vector gate-level simulation and post-simulation;

?       Can establish a reliable test mode for SDC constraints and target for timing signoff

Big Plus：

?       Experience of SDC constraint design, Synthesis, Formal and STA.

?       Experience of ATE test pattern debugging with ATE machine.

?       Experience of Load board and Probe-card solution design

?       Experience of CPF flow and verification

Experience of self-built logic BIST design for core logic module, etc.

  

StarFive是基于免费且开放的RISC-V指令集架构的商业化处理器核心IP、开发工具和芯片解决方案的领导者。 在RISC-V开创者和业内资深专家组成的团队领导下，StarFive帮助SoC设计人员缩短产品上市时间，以及通过定制的开放式架构处理器内核降低成本，同时，使系统设计人员能够构建基于RISC-V的定制半导体，从而实现芯片优化。

上海赛昉科技有限公司成立于2018年8月24日，公司基于RISC-V的开源生态并在RISC-V开创者和业内资深专家组成的团队领导下，利用领先的RISC-V内核定制技术和敏捷设计方法，成为具有国内自主可控，有龙头作用的RISC-V解决方案提供商；同时利用自主知识产权针对AI-IOT的关键应用领域，通过平台化、模板化的设计理念，实现垂直领域的核心技术整合，提供相关领域的系列化芯片及其解决方案，创造一种新的商业模式，成为对应领域的技术主导者和芯片与方案的主流供应商。