北京招聘

Responsibilities:

– Set up RISC-V CPU verification Env, including SystemVerilog Env, SystemC Env and ASM test cases Env.

– Verification of RISC-V scalar and vector machine functional blocks according to design SPEC.

– Performance evaluation of RISC-V scalar and vector implementations.

– Design and implement configurable and synthesizable monitor and analysis blocks along with design team.

Qualifications:

– BS degree in CS, EE, and Automation, or qeuivalent practical experience. MS and PhD preferred.

– 5+ years' experience in CPU/SoC verifications.

– Deep understanding of verification flow and theory, not noly existing AMBA based verfication.

– Experience of design test cases and ASM program to trigger deep hardware logic, should with well understanding of CPU architecture.

– Experience of random test case generation and evaluation.

Big Plus:

– Experience with Chisel, Scala or functionaly languages.

– Compiler experience with custom instructions.

  

StarFive是基于免费且开放的RISC-V指令集架构的商业化处理器核心IP、开发工具和芯片解决方案的领导者。 在RISC-V开创者和业内资深专家组成的团队领导下，StarFive帮助SoC设计人员缩短产品上市时间，以及通过定制的开放式架构处理器内核降低成本，同时，使系统设计人员能够构建基于RISC-V的定制半导体，从而实现芯片优化。

上海赛昉科技有限公司成立于2018年8月24日，公司基于RISC-V的开源生态并在RISC-V开创者和业内资深专家组成的团队领导下，利用领先的RISC-V内核定制技术和敏捷设计方法，成为具有国内自主可控，有龙头作用的RISC-V解决方案提供商；同时利用自主知识产权针对AI-IOT的关键应用领域，通过平台化、模板化的设计理念，实现垂直领域的核心技术整合，提供相关领域的系列化芯片及其解决方案，创造一种新的商业模式，成为对应领域的技术主导者和芯片与方案的主流供应商。