北京招聘

Position Summary:

- Top-level digital architecture planning including partition and interface to register maps.

- State machine; SPI, I2C, interface; Digital Filter RTL design.

- Verilog HDL based digital design: verification, synthesis, simulation and static timing analysis.

- Design for test including scan insertion, test pattern generation.

- FPGA prototype verification.

- Assisting support of customer applications.

Requirements:

- BSEE/MSEE/PhD with digital design experience

- Familiar with verilog and RTL design

- Familiar with ASIC design flow and IC design tools such as VCS,DC,PT etc.

- Familiar with digital signal processing knowledge is a plus

- Experience with design prototyping and validation using FPGAs

- Good problem solving and Ability to work independently.

- Good writing and communication skills.

  

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