Front End Design Engineer
超威半导体(中国)有限公司
- 公司规模:1000-5000人
- 公司性质:外资(欧美)
- 公司行业:电子技术/半导体/集成电路
职位信息
- 发布日期:2019-03-25
- 工作地点:上海-浦东新区
- 招聘人数:1人
- 工作经验:5-7年经验
- 学历要求:本科
- 职位类别:集成电路IC设计/应用工程师 IC验证工程师
职位描述
RESPONSIBILITIES:
· Understand the architecture of the graphics IP and functional block being designed
· Build C/C++ model for simulation
· Build test bench and monitors for DUT
· Compose test plan and validation vectors to ensure functional completeness
· Debug function/performance bugs of graphics IP
· Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation
· Focus on physical design of deep sub-micron GPU chips including block level (full chip) floor planning, timing closure, place&route, physical verification etc
REQUIREMENTS:
· Have in depth knowledge of entire design process from Design specification, defining architecture, micro-architecture, RTL design and functional verification, synthesis, Physical Design, Timing closure, Tape-out, and post-Si debug.
· Have hands-on experience in Chiplevel Design/Integration activities.
· Some Physical Design exposure required.
· Perform Synthesis and netlisting tasks such as SDC Development, Scan Insertion, ECO implementation, Formal Verification, etc.
· Some exposure to DFT is a strong plus.
· Work with Physical Design team on Floor Plan, budgeting, timing closure, Signal Integrity, ECO flows, Power analysis, IO PAD placement, etc.
· Should have expertise in: Cadence RTL Compiler, Design Compiler, PrimeTime, Conformal LEC. Good knowledge of datapath compilers is required.
· Expertise in Perl and Tcl is a must.
· Knowledge of chip bus interfaces such as AHB and various standard peripherals & interfaces is a plus.
· Should be able to work closely with RTL Designers and Backend Physical Design teams across multiple sites.
· Must have good communication & Analytical thinking skills.
· Should have proficiency in flow development and scripting.
· Should be able to Lead a team, and provide Technical mentoring and guidance to junior engineers.
EDUCATION:
· Master with at least 5 years or Bachelor with at least 8 years working experience in ASIC area
职能类别: 集成电路IC设计/应用工程师 IC验证工程师
公司介绍
联系方式
- Email:bella.yu@amd.com
- 公司地址:上海-浦东新区 张江 环科路669号凯瑞大厦