Design Verification Engineer (Methodology)
超威半导体(中国)有限公司
- 公司规模:1000-5000人
- 公司性质:外资(欧美)
- 公司行业:电子技术/半导体/集成电路
职位信息
- 发布日期:2019-03-29
- 工作地点:上海-浦东新区
- 招聘人数:若干人
- 工作经验:无工作经验
- 学历要求:招若干人
- 语言要求:不限
- 职位类别:集成电路IC设计/应用工程师
职位描述
AMD Verification Methodology and Technology (VMT) team delivers verification methodology and technology for AMD all teams and products. You'll be working with the global team on the verification methodologies and technologies covering logic design technology, logic function verification technology, logic static check and sign-off technology, low power technology, DFX (SMS) technology and complex system design description and automation methodologies.
Job Responsibilities:
? Logic design technology and methodology research and development
? RTL static check and sign-off technology and methodology research and development (Lint, CDC, Formal, LEC, DC)
? Collaborate with EDA vendors for tool trainings, evaluation and deployment
? Provide training and collaborate with AMD company-wide groups for methodology deployment
Job Requirements:
? Major in EE, CS or related, Master Degree or Bachelor with 3+ years working experiences
? Familiar with Linux Environment (including command shell scripting)
? Skillful at script language like Ruby, Perl, Python or Tcl
? Be good at C/C++ programming
? Excellent communication skills (both written and oral)
? Strong problem solving skills
? Good knowledge on verification methodology
? Be versatile in any one of the verification methodology like UVM as well as knowledge of industry standard tools for verification is a plus
职能类别: 集成电路IC设计/应用工程师
公司介绍
联系方式
- Email:bella.yu@amd.com
- 公司地址:上海-浦东新区 张江 环科路669号凯瑞大厦