PMTS ASIC Design Engineer (Memory control)
超威半导体(中国)有限公司
- 公司规模:1000-5000人
- 公司性质:外资(欧美)
- 公司行业:电子技术/半导体/集成电路
职位信息
- 发布日期:2019-03-29
- 工作地点:上海-浦东新区
- 招聘人数:若干人
- 工作经验:无工作经验
- 学历要求:招若干人
- 语言要求:不限
- 职位类别:高级硬件工程师 集成电路IC设计/应用工程师
职位描述
RESPONSIBILITIES:
? Oversees definition, design, verification, and documentation for ASIC development.
? Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation.
? Contributes to the development of multidimensional designs involving the layout of complex integrated circuits.
? Evaluates all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use.
? Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. May also review vendor capability to support development.
REQUIREMENTS:
? Power targets, IP selection, floorplan review etc.
? Develop RTL code for chip level in Verilog HDL and make sure functional correct and reusable for different configuration.
? Synthesis Participate in SOC IC project logic design
? Working with architect to define chip level specification, including clock and deliver netlist that meeting timing, area and power requirement. Help PD on the floorplanning and close timing.
? Work very closely with physical design engineers to help on floorplan, timing closure, power design validation and etc.
? Bring-up ASIC.
? Guide hardware team to solve design problem in application.
? Help to short Time-To-Market.
? Is required to undertake high-level technical assignments with strategic impact.
? Synthesizes marketing requirement, technology and implementation.
? Contributes to the development of product strategy and provides technical leadership in the development of new products, processes or technologies in support of this strategy.
? Represents the key technology resource to a large engineering team or group.
? Contributes technology leadership for multiple projects and collaborates with marketing to develop the right technology and business choices.
? Typically contributes across projects within product groups or technology development initiatives.
? Provides technical leadership; may have limited management accountability for a small number of engineers related to projects, (e.g., interview and selection, day-to-day technical supervision or mentoring)
EDUCATION:
? BS + 9 years or MS + 7 years or PhD + 5 years
? Generates publication(s) relevant to areas of expertise
职能类别: 高级硬件工程师 集成电路IC设计/应用工程师
公司介绍
联系方式
- Email:bella.yu@amd.com
- 公司地址:上海-浦东新区 张江 环科路669号凯瑞大厦