北京招聘

岗位职责:

*Normal Tasks
* Develop DV test benches for IP or sub system/SOC verification
* Determine simulation requirements at architecture, logic design specifications
* Developed test plan for different type of verification, formal, gate-level, power and performance
* Execution of test cases development for design completeness in different targeted usage models
* Project deliverables include verification documents, simulation models, test benches, and associated documentation and additional collateral
* Deliverables include TB, Coverage and Closure for full completeness
* Coach/Guide/Mentor engineer in technical manner
* Look forward, resource and task planning to ensure schedule targets
* Sense of urgency

任职资格:

*General
*A successful DV candidate will be detail oriented with solid analytic and debugging skills, strong knowledge of digital design, good understanding of Object Oriented Programming (OOP) concepts and good communication skills. Experienced SystemVerilog testbench (UVM) and Verilog writer. Experienced in power and performance verification. Skilled in common programming language like C, C++, Shell, Perl are required
Willingness to learn and ability to take initiatives. Effective but not compromising on details. Team player. Ability to coach and provide guidance to team members.
*EE OR CS major degree with over 8 years of DV experience in direct experience in highly complex SOC ASIC verification tasks. At least 2-3 years of hands-on technical management experience
*MSEE is preferred

紫光展锐是我国集成电路设计产业的龙头企业，作为未来数字世界的生态承载者，以生态为核心战略，高举5G和AI两面技术旗帜，深耕三大业务领域：消费电子业务为个人的智能化需要服务、工业电子业务支撑工业体系和社会智能化，泛连接业务探索充满创新的新网络领域。
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紫光展锐曾五次获得国家科技进步奖，其中特等奖1次、一等奖2次，已申请专利超过4000项，拥有3G/4G/5G、多卡多待、多模等核心专利。
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