北京招聘

工作职责:

1. Work closely with the SoC design team on understanding the embedded system features being designed;

2. Develop and execute test plans for system level functional features related to CPU, BUS, CLOCK, RESET, Memory Controller, Power Management, etc.

3. Design, implement and improve verification testbench in Verilog, System-Verilog, UVM, C;

4. Develop and refine test libraries, model and test cases;

5. Apply functional coverage/assertion into testbench as enhancement;

任职资格:

1. Excellent background in ASIC SOC design and verification.

2. Good knowledge of the embedded systems.

3. Good at Verilog, Systemverilog, UVM

4. At least five years working experience with verilog logic design language.

5. Experience with Cadence or Synopsys simulator.

6. Working experience with C and C++ is preferred.

7. Experience in GCC/G++, GDB and shell "script"s (C_SHELL, TCL, PERL) is also preferred.

8. Self-motivated and good team player.

微信分享