北京招聘

Job Description:

1. Be a part of the Central Engineering AMS IP team at Marvell china.
2. Main responsibility is perform analog layout and related drc/lvs/erc/ant verification, debugging and violations fix.
3. Will be responsible for all levels of analog/mixed-signal layout from block level up to the AFE most top level integration and physical verification.

    

    

Job Qualifications:

    

1. BS degree of electronic engineering, computer science with 5 years’ experience in IC layout
2. Be familiar in high frequency analog/mixed-signal layout methods.
3. Be familiar with 16nm/12nm finfet technology, experience in 7nm finfet is preferred
4. Be familiar with cadence virtuoso, synopsys laker and calibre drc/lvs.
5. Good communication skills in written and spoken English.
6. Good team work and communication skills. Hardworking and self-motivated under a high competition IP team.
7. Good understanding of layout impact on device matching, noise coupling from signal, supply and substrate.
8. Good understanding the importance of signal flow, power/ground structure and block placement in layout floorplan.
9. Be familiar with SKILL/Perl/TCL program is preferred.

We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you. Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.

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