北京招聘

Job Description

ASIC design engineer responsible for post RTL design flow including synthesis, timing closure, DFT and physical design flow. He or she will be responsible for block and/or chip level synthesis, timing closure, DFT, physical design, and integration.

Qualifications

1.MSEE w/ 5-8 year experience in developing and implementing ASIC products.

2.Must have good post-RTL experience including synthesis, timing analysis, and physical design. Good understanding of block and top-level physical timing closure. Flexible to move between all post-RTL designs activities as required. Able to perform custom placement and routing for mixed-signal designs.

3.Must be proficient in the following skills:

-Logic or physical synthesis using Synopsys or Cadence tools

-DFT generation and verification

- Static timing analysis using Primetime

-Physical design for 28nm and beyond

-Strong Perl and Tcl scripting skill

4.Highly desirable skills:

-Low power design

-Circuit level or custom design experience

-Floorplanning, clock-tree synthesis and power planning/analysis

-Signal integrity and physical verification

5.Good personal communication skills and team working spirit. Hardworking and motivated to be part of a highly competent design team.

We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you. Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.

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