北京招聘

Develop, implement and verify state-of-the-art Design for Test (DFT) architectures

Setup and implement DFT insertion flow

SAF, TDF, OCC, Scan Compression, MBIST, BISR, Logic BIST, JTAG

Perform ATPG analysis and pattern generation

RTL, Gate, and timing back-annotated simulation 

Participate in test plan and coverage reviews 

Participate in Silicon debug and write scripts to effectively handle ATE related data

Contribute to the continuous development of our DFT methodology

Communicate and work with team members across multiple disciplines

任职要求：

MSEE or equivalent

2+ years working experience in the EE industry

Understanding of ASIC design flow and DFT concept.

Proficiency with Synopsys DFT Compiler, Mentor Tessent MemBIST, and TestKompress Tool

Scripting skills: TCL, Perl, Python, etc 

Practical Experience with SOC design and RTL development 

Knowledge of STA constraints

Experience with large gate-level simulation setup and debug

Practical experience with silicon debug

Ability to multi-task, set priorities, and works in a strong team environment

Excellent verbal and written communication skills 

Positive, self-motivated and excited to learn new skills, tools, IP, and design flows 

We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you. Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.

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