北京招聘

职位描述：
? Logic synthesis: including memory replacement, RTL sanity check, std. cell mapping, timing, power, and area optimization, scan stitching, formal verification and signoff.
? Design for test: including DFT spec and partition, BSD/JTAG/MBIST logic generation and insertion, scan chain insertion and pattern generation, simulation and verification, DFT SDC file deliver.
? Physical implementation: including floorplan, power routing, placement, clock tree synthesis, timing closure, routing, si fixing, drc fixing, dfm ...etc
? Physical verification: including low power check, timing analysis, timing eco, xtalk analysis, power analysis, ESD analysis, EM analysis, drc check, lvs check, ant check, erc check ...etc
? Tapeout: timing signoff, power signoff, design tapeout... etc


Job Requirement
? BS or MS in EE or CS from a good university, major in VLSI, logic or CPU design. Good GPA required.
? Hands-on experience in IC design industry or in college is preferred.
? Detail oriented, self-motivated and team player. Good verbal and written communication skills.
? To qualify for the job, you should have some or all of the following technical background:
a. Working knowledge of HDL, such as Verilog , frontend design or SOC integration
       experience, including synthesis, timing analysis, timing constraint creation, and
       formal verification. Experience in Design-for-test (DFT), with JTAG, BIST and
       SCAN.
b. Working knowledge of LEF/DEF and backend physical design, such as floorplanning, standard cell placement and routing or layout integration.
c. Understanding of SPICE model and transistor circuits, and standard cell layouts.
d. IC design methodologies using design automation EDA tools, ASIC design flow, and deep sub-micron technology issues.
e. Familiarization with scripting programming, such as Tcl or Perl. Experience with
       makefile and understanding of the design automation for efficiency.
f. Working experience with any of the EDA tools listed below:
       i. Synopsys: IC Compiler, StartRC, PrimeTime, PT-SI, PrimeRail, Formality,
                   Hercules, Design Compiler, TetraMAX)
       ii. Cadence: EDI, SOC Encounter, Nanoroute, Celtic, Verplex, RC
       iii. Magma: Talus, Blast
       iv. Mentor: Calibre, TestKompress, FastScan, MBIST, BSD
       v. Ansys: Apache Redhawk 举报 分享

   北京盛源达科技有限公司（SYD Technology）成立于IoT刚兴起的2012年初，由具有丰富无线通信芯片设计经验的海归团队和本土精英组建而成，专注于超低功耗物联网无线通信系统芯片设计、开发、制造和销售。产品包括：超低功耗嵌入式蓝牙BLE SoC(Cortex M0)、超低功耗嵌入式WiFi SoC(Cortex M4)。
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