北京招聘

职位描述：
建立
Job Description
External Description
? Logic synthesis: including memory replacement, RTL sanity check, std. cell mapping, timing, power, and area optimization, scan stitching, formal verification and signoff.
? Design for test: including DFT spec and partition, BSD/JTAG/MBIST logic generation and insertion, scan chain insertion and pattern generation, simulation and verification, DFT SDC file deliver.
? Physical implementation: including floorplan, power routing, placement, clock tree synthesis, timing closure, routing, si fixing, drc fixing, dfm ...etc
? Physical verification: including low power check, timing analysis, timing eco, xtalk analysis,power analysis, ESD analysis, EM analysis, drc check, lvs check, ant check, erc check ...etc
? Tapeout: timing signoff, power signoff, design tapeout... etc
Qualifications – External
? BS or MS in EE or CS from a good university, major in VLSI, logic or CPU design. Good GPA required.
? Hands-on experience in IC design industry or in college is preferred.
? Detail oriented, self-motivated and team player. Good verbal and written communication skills.
? To qualify for the job, you should have some or all of the following technical background:
a. Working knowledge of HDL, such as Verilog , frontend design or SOC integration
       experience, including synthesis, timing analysis, timing constraint creation, and
       formal verification. Experience in Design-for-test (DFT), with JTAG, BIST and
       SCAN.
b. Working knowledge of LEF/DEF and backend physical design, such as floorplanning, standard cell placement and routing or layout integration.
c. Understanding of SPICE model and transistor circuits, and standard cell layouts.
d. IC design methodologies using design automation EDA tools, ASIC design flow, and deep sub-micron technology issues.
e. Familiarization with scripting programming, such as Tcl or Perl. Experience with
       makefile and understanding of the design automation for efficiency.
f. Working experience with any of the EDA tools listed below:
       i. Synopsys: IC Compiler, StartRC, PrimeTime, PT-SI, PrimeRail, Formality,
                   Hercules, Design Compiler, TetraMAX)
       ii. Cadence: EDI, SOC Encounter, Nanoroute, Celtic, Verplex, RC
       iii. Magma: Talus, Blast
       iv. Mentor: Calibre, TestKompress, FastScan, MBIST, BSD
       v. Ansys: Apache Redhawk
Internal Description
? Work with the product design group to provide front- and/or back-end design service for multiple Marvell SOC design groups, with various challenging designs, such as low power, high speed requirements advance technology or ultra-compact die size designs.
? Perform some or all of the IC design and implementation, such as design integration, logic synthesis, timing analysis, design for test, physical layout floor planning, power grid design, automatic standard cell placement and routing (APR), clock tree synthesis (CTS), timing closure, power and signal integrity analysis (IR-Drop and EM analysis), layout physical verification (DRC/LVS/Antenna). 举报 分享

We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you. Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.

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